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-rw-r--r--gpu_renderer/src/command_buffer.rs2
-rw-r--r--gpu_renderer/src/lib.rs2
2 files changed, 2 insertions, 2 deletions
diff --git a/gpu_renderer/src/command_buffer.rs b/gpu_renderer/src/command_buffer.rs
index 1f5b98a..b6c7005 100644
--- a/gpu_renderer/src/command_buffer.rs
+++ b/gpu_renderer/src/command_buffer.rs
@@ -89,7 +89,7 @@ impl CommandBufferBuilder {
     pub fn e_clear(&mut self, buffers: u32, color: [f32; 4], depth: f64, stencil: u32) {
         self.push_cmd(VIRGL_CCMD_CLEAR, 0, VIRGL_OBJ_CLEAR_SIZE);
         self.push(buffers);
-        for &c in color.iter() {
+        for c in &color {
             self.push(c.to_bits())
         }
         self.push_qw(depth.to_bits());
diff --git a/gpu_renderer/src/lib.rs b/gpu_renderer/src/lib.rs
index caa9f8e..8d03673 100644
--- a/gpu_renderer/src/lib.rs
+++ b/gpu_renderer/src/lib.rs
@@ -792,7 +792,7 @@ impl Resource {
         }
         self.detach_backing();
         self.backing_mem = Some(mem.clone());
-        for &(addr, len) in iovecs.iter() {
+        for &(addr, len) in iovecs {
             // Unwrap will not panic because we already checked the slices.
             let slice = mem.get_slice(addr.offset(), len as u64).unwrap();
             self.backing_iovecs.push(VirglVec {