diff options
Diffstat (limited to 'devices')
| -rw-r--r-- | devices/src/ioapic.rs | 38 | ||||
| -rw-r--r-- | devices/src/pic.rs | 6 | ||||
| -rw-r--r-- | devices/src/register_space/register.rs | 16 | ||||
| -rw-r--r-- | devices/src/usb/xhci/event_ring.rs | 27 | ||||
| -rw-r--r-- | devices/src/usb/xhci/interrupter.rs | 52 | ||||
| -rw-r--r-- | devices/src/usb/xhci/scatter_gather_buffer.rs | 34 | ||||
| -rw-r--r-- | devices/src/virtio/gpu/mod.rs | 8 |
7 files changed, 82 insertions, 99 deletions
diff --git a/devices/src/ioapic.rs b/devices/src/ioapic.rs index d8b3808..0e9c89b 100644 --- a/devices/src/ioapic.rs +++ b/devices/src/ioapic.rs @@ -261,27 +261,25 @@ impl Ioapic { return; } - { - let entry = &mut self.redirect_table[index]; - if is_high_bits { - entry.set(32, 32, val.into()); - } else { - let before = *entry; - entry.set(0, 32, val.into()); - - // respect R/O bits. - entry.set_delivery_status(before.get_delivery_status()); - entry.set_remote_irr(before.get_remote_irr()); - - // Clear remote_irr when switching to edge_triggered. - if entry.get_trigger_mode() == TriggerMode::Edge { - entry.set_remote_irr(false); - } - - // NOTE: on pre-4.0 kernels, there's a race we would need to work around. - // "KVM: x86: ioapic: Fix level-triggered EOI and IOAPIC reconfigure race" - // is the fix for this. + let entry = &mut self.redirect_table[index]; + if is_high_bits { + entry.set(32, 32, val.into()); + } else { + let before = *entry; + entry.set(0, 32, val.into()); + + // respect R/O bits. + entry.set_delivery_status(before.get_delivery_status()); + entry.set_remote_irr(before.get_remote_irr()); + + // Clear remote_irr when switching to edge_triggered. + if entry.get_trigger_mode() == TriggerMode::Edge { + entry.set_remote_irr(false); } + + // NOTE: on pre-4.0 kernels, there's a race we would need to work around. + // "KVM: x86: ioapic: Fix level-triggered EOI and IOAPIC reconfigure race" + // is the fix for this. } // TODO(mutexlox): route MSI. diff --git a/devices/src/pic.rs b/devices/src/pic.rs index 33106ef..9b8235f 100644 --- a/devices/src/pic.rs +++ b/devices/src/pic.rs @@ -724,10 +724,8 @@ mod tests { // OCW2: Set rotate on auto EOI. data.pic.write(PIC_SECONDARY_COMMAND, &[0x80]); - { - let secondary_pic = &data.pic.pics[PicSelect::Secondary as usize]; - assert!(secondary_pic.rotate_on_auto_eoi); - } + let secondary_pic = &data.pic.pics[PicSelect::Secondary as usize]; + assert!(secondary_pic.rotate_on_auto_eoi); // OCW2: Clear rotate on auto EOI. data.pic.write(PIC_SECONDARY_COMMAND, &[0x00]); diff --git a/devices/src/register_space/register.rs b/devices/src/register_space/register.rs index 160412c..268b945 100644 --- a/devices/src/register_space/register.rs +++ b/devices/src/register_space/register.rs @@ -259,15 +259,13 @@ impl<T: RegisterValue> RegisterInterface for Register<T> { let total_size = (overlap.to - overlap.from) as usize + 1; let mut reg_value: T = self.lock().value; - { - let value: &mut [u8] = reg_value.as_mut_slice(); - for i in 0..total_size { - value[my_start_idx + i] = self.apply_write_masks_to_byte( - value[my_start_idx + i], - data[write_start_idx + i], - my_start_idx + i, - ); - } + let value: &mut [u8] = reg_value.as_mut_slice(); + for i in 0..total_size { + value[my_start_idx + i] = self.apply_write_masks_to_byte( + value[my_start_idx + i], + data[write_start_idx + i], + my_start_idx + i, + ); } // A single u64 register is done by write to lower 32 bit and then higher 32 bit. Callback diff --git a/devices/src/usb/xhci/event_ring.rs b/devices/src/usb/xhci/event_ring.rs index 0b35ef7..4b510f1 100644 --- a/devices/src/usb/xhci/event_ring.rs +++ b/devices/src/usb/xhci/event_ring.rs @@ -89,20 +89,19 @@ impl EventRing { fence(Ordering::SeqCst); trb.set_cycle_bit(self.producer_cycle_state); - { - // Offset of cycle state byte. - const CYCLE_STATE_OFFSET: usize = 12usize; - let data = trb.as_slice(); - // Trb contains 4 dwords, the last one contains cycle bit. - let cycle_bit_dword = &data[CYCLE_STATE_OFFSET..]; - let address = self.enqueue_pointer; - let address = address - .checked_add(CYCLE_STATE_OFFSET as u64) - .ok_or(Error::BadEnqueuePointer(self.enqueue_pointer))?; - self.mem - .write_all_at_addr(cycle_bit_dword, address) - .map_err(Error::MemoryWrite)?; - } + + // Offset of cycle state byte. + const CYCLE_STATE_OFFSET: usize = 12usize; + let data = trb.as_slice(); + // Trb contains 4 dwords, the last one contains cycle bit. + let cycle_bit_dword = &data[CYCLE_STATE_OFFSET..]; + let address = self.enqueue_pointer; + let address = address + .checked_add(CYCLE_STATE_OFFSET as u64) + .ok_or(Error::BadEnqueuePointer(self.enqueue_pointer))?; + self.mem + .write_all_at_addr(cycle_bit_dword, address) + .map_err(Error::MemoryWrite)?; usb_debug!( "event write to pointer {:#x}, trb_count {}, {}", diff --git a/devices/src/usb/xhci/interrupter.rs b/devices/src/usb/xhci/interrupter.rs index e850eb2..a896fb4 100644 --- a/devices/src/usb/xhci/interrupter.rs +++ b/devices/src/usb/xhci/interrupter.rs @@ -83,14 +83,12 @@ impl Interrupter { /// Send port status change trb for port. pub fn send_port_status_change_trb(&mut self, port_id: u8) -> Result<()> { let mut trb = Trb::new(); - { - let psctrb = trb - .cast_mut::<PortStatusChangeEventTrb>() - .map_err(Error::CastTrb)?; - psctrb.set_port_id(port_id); - psctrb.set_completion_code(TrbCompletionCode::Success as u8); - psctrb.set_trb_type(TrbType::PortStatusChangeEvent as u8); - } + let psctrb = trb + .cast_mut::<PortStatusChangeEventTrb>() + .map_err(Error::CastTrb)?; + psctrb.set_port_id(port_id); + psctrb.set_completion_code(TrbCompletionCode::Success as u8); + psctrb.set_trb_type(TrbType::PortStatusChangeEvent as u8); self.add_event(trb) } @@ -102,17 +100,15 @@ impl Interrupter { trb_addr: GuestAddress, ) -> Result<()> { let mut trb = Trb::new(); - { - let ctrb = trb - .cast_mut::<CommandCompletionEventTrb>() - .map_err(Error::CastTrb)?; - ctrb.set_trb_pointer(trb_addr.0); - ctrb.set_command_completion_parameter(0); - ctrb.set_completion_code(completion_code as u8); - ctrb.set_trb_type(TrbType::CommandCompletionEvent as u8); - ctrb.set_vf_id(0); - ctrb.set_slot_id(slot_id); - } + let ctrb = trb + .cast_mut::<CommandCompletionEventTrb>() + .map_err(Error::CastTrb)?; + ctrb.set_trb_pointer(trb_addr.0); + ctrb.set_command_completion_parameter(0); + ctrb.set_completion_code(completion_code as u8); + ctrb.set_trb_type(TrbType::CommandCompletionEvent as u8); + ctrb.set_vf_id(0); + ctrb.set_slot_id(slot_id); self.add_event(trb) } @@ -127,16 +123,14 @@ impl Interrupter { endpoint_id: u8, ) -> Result<()> { let mut trb = Trb::new(); - { - let event_trb = trb.cast_mut::<TransferEventTrb>().map_err(Error::CastTrb)?; - event_trb.set_trb_pointer(trb_pointer); - event_trb.set_trb_transfer_length(transfer_length); - event_trb.set_completion_code(completion_code as u8); - event_trb.set_event_data(event_data.into()); - event_trb.set_trb_type(TrbType::TransferEvent as u8); - event_trb.set_endpoint_id(endpoint_id); - event_trb.set_slot_id(slot_id); - } + let event_trb = trb.cast_mut::<TransferEventTrb>().map_err(Error::CastTrb)?; + event_trb.set_trb_pointer(trb_pointer); + event_trb.set_trb_transfer_length(transfer_length); + event_trb.set_completion_code(completion_code as u8); + event_trb.set_event_data(event_data.into()); + event_trb.set_trb_type(TrbType::TransferEvent as u8); + event_trb.set_endpoint_id(endpoint_id); + event_trb.set_slot_id(slot_id); self.add_event(trb) } diff --git a/devices/src/usb/xhci/scatter_gather_buffer.rs b/devices/src/usb/xhci/scatter_gather_buffer.rs index c05afd5..da43b33 100644 --- a/devices/src/usb/xhci/scatter_gather_buffer.rs +++ b/devices/src/usb/xhci/scatter_gather_buffer.rs @@ -132,31 +132,29 @@ mod test { fn scatter_gather_buffer_test() { let gm = GuestMemory::new(&vec![(GuestAddress(0), 0x1000)]).unwrap(); let mut td = TransferDescriptor::new(); + // In this td, we are going to have scatter buffer at 0x100, length 4, 0x200 length 2 and // 0x300 length 1. + let mut trb = Trb::new(); - { - let ntrb = trb.cast_mut::<NormalTrb>().unwrap(); - ntrb.set_trb_type(TrbType::Normal as u8); - ntrb.set_data_buffer(0x100); - ntrb.set_trb_transfer_length(4); - } + let ntrb = trb.cast_mut::<NormalTrb>().unwrap(); + ntrb.set_trb_type(TrbType::Normal as u8); + ntrb.set_data_buffer(0x100); + ntrb.set_trb_transfer_length(4); td.push(AddressedTrb { trb, gpa: 0 }); + let mut trb = Trb::new(); - { - let ntrb = trb.cast_mut::<NormalTrb>().unwrap(); - ntrb.set_trb_type(TrbType::Normal as u8); - ntrb.set_data_buffer(0x200); - ntrb.set_trb_transfer_length(2); - } + let ntrb = trb.cast_mut::<NormalTrb>().unwrap(); + ntrb.set_trb_type(TrbType::Normal as u8); + ntrb.set_data_buffer(0x200); + ntrb.set_trb_transfer_length(2); td.push(AddressedTrb { trb, gpa: 0 }); + let mut trb = Trb::new(); - { - let ntrb = trb.cast_mut::<NormalTrb>().unwrap(); - ntrb.set_trb_type(TrbType::Normal as u8); - ntrb.set_data_buffer(0x300); - ntrb.set_trb_transfer_length(1); - } + let ntrb = trb.cast_mut::<NormalTrb>().unwrap(); + ntrb.set_trb_type(TrbType::Normal as u8); + ntrb.set_data_buffer(0x300); + ntrb.set_trb_transfer_length(1); td.push(AddressedTrb { trb, gpa: 0 }); let buffer = ScatterGatherBuffer::new(gm.clone(), td).unwrap(); diff --git a/devices/src/virtio/gpu/mod.rs b/devices/src/virtio/gpu/mod.rs index 686c174..2c13acc 100644 --- a/devices/src/virtio/gpu/mod.rs +++ b/devices/src/virtio/gpu/mod.rs @@ -690,11 +690,9 @@ impl VirtioDevice for Gpu { let offset = offset as usize; let len = data.len(); let mut cfg = self.get_config(); - { - let cfg_slice = cfg.as_mut_slice(); - if offset + len <= cfg_slice.len() { - cfg_slice[offset..offset + len].copy_from_slice(data); - } + let cfg_slice = cfg.as_mut_slice(); + if offset + len <= cfg_slice.len() { + cfg_slice[offset..offset + len].copy_from_slice(data); } if (cfg.events_clear.to_native() & VIRTIO_GPU_EVENT_DISPLAY) != 0 { self.config_event = false; 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