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Diffstat (limited to 'devices/src/usb/xhci')
-rw-r--r--devices/src/usb/xhci/ring_buffer.rs23
1 files changed, 10 insertions, 13 deletions
diff --git a/devices/src/usb/xhci/ring_buffer.rs b/devices/src/usb/xhci/ring_buffer.rs
index 2f66fa8..5e2c570 100644
--- a/devices/src/usb/xhci/ring_buffer.rs
+++ b/devices/src/usb/xhci/ring_buffer.rs
@@ -67,19 +67,16 @@ impl RingBuffer {
     pub fn dequeue_transfer_descriptor(&mut self) -> Result<Option<TransferDescriptor>> {
         let mut td: TransferDescriptor = TransferDescriptor::new();
         while let Some(addressed_trb) = self.get_current_trb()? {
-            match addressed_trb.trb.trb_type() {
-                Ok(TrbType::Link) => {
-                    let link_trb = addressed_trb
-                        .trb
-                        .cast::<LinkTrb>()
-                        .map_err(Error::CastTrb)?;
-                    self.dequeue_pointer = GuestAddress(link_trb.get_ring_segment_pointer());
-                    self.consumer_cycle_state =
-                        self.consumer_cycle_state != link_trb.get_toggle_cycle_bit();
-                    continue;
-                }
-                _ => {}
-            };
+            if let Ok(TrbType::Link) = addressed_trb.trb.trb_type() {
+                let link_trb = addressed_trb
+                    .trb
+                    .cast::<LinkTrb>()
+                    .map_err(Error::CastTrb)?;
+                self.dequeue_pointer = GuestAddress(link_trb.get_ring_segment_pointer());
+                self.consumer_cycle_state =
+                    self.consumer_cycle_state != link_trb.get_toggle_cycle_bit();
+                continue;
+            }
 
             self.dequeue_pointer = match self.dequeue_pointer.checked_add(size_of::<Trb>() as u64) {
                 Some(addr) => addr,