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author | Daniel Prilik <prilik@google.com> | 2019-02-26 17:28:26 -0800 |
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committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-08 21:20:53 -0800 |
commit | df4cf17d56d9c5cff45868c48155a6f919be5555 (patch) | |
tree | 1aaf7f3c186e4e2191fcb4168caf6a427953dc02 /devices | |
parent | b0f54b90207e914a5399b0b58dd22f4c3d4dde52 (diff) | |
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devices: PCI: fix underflow for 64 bit BAR config
underflow occurs when configuring a 64 bit register with a <33 bit address. BUG=chromium:924405 TEST=boot VM Change-Id: I53a309b7bff3c91012bacb12d9fc9f8ceed68699 Reviewed-on: https://chromium-review.googlesource.com/1493011 Commit-Ready: Daniel Prilik <prilik@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-by: Zach Reizner <zachr@chromium.org>
Diffstat (limited to 'devices')
-rw-r--r-- | devices/src/pci/pci_configuration.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/devices/src/pci/pci_configuration.rs b/devices/src/pci/pci_configuration.rs index ee46e38..3aac1c8 100644 --- a/devices/src/pci/pci_configuration.rs +++ b/devices/src/pci/pci_configuration.rs @@ -382,7 +382,7 @@ impl PciConfiguration { } self.registers[bar_idx + 1] = (config.addr >> 32) as u32; - self.writable_bits[bar_idx + 1] = !((config.size >> 32) - 1) as u32; + self.writable_bits[bar_idx + 1] = !((config.size >> 32).wrapping_sub(1)) as u32; self.bar_used[config.reg_idx + 1] = true; } } |