From df4cf17d56d9c5cff45868c48155a6f919be5555 Mon Sep 17 00:00:00 2001
From: Daniel Prilik <prilik@google.com>
Date: Tue, 26 Feb 2019 17:28:26 -0800
Subject: devices: PCI: fix underflow for 64 bit BAR config

underflow occurs when configuring a 64 bit register with a <33 bit
address.

BUG=chromium:924405
TEST=boot VM

Change-Id: I53a309b7bff3c91012bacb12d9fc9f8ceed68699
Reviewed-on: https://chromium-review.googlesource.com/1493011
Commit-Ready: Daniel Prilik <prilik@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Reviewed-by: Zach Reizner <zachr@chromium.org>
---
 devices/src/pci/pci_configuration.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'devices')

diff --git a/devices/src/pci/pci_configuration.rs b/devices/src/pci/pci_configuration.rs
index ee46e38..3aac1c8 100644
--- a/devices/src/pci/pci_configuration.rs
+++ b/devices/src/pci/pci_configuration.rs
@@ -382,7 +382,7 @@ impl PciConfiguration {
                 }
 
                 self.registers[bar_idx + 1] = (config.addr >> 32) as u32;
-                self.writable_bits[bar_idx + 1] = !((config.size >> 32) - 1) as u32;
+                self.writable_bits[bar_idx + 1] = !((config.size >> 32).wrapping_sub(1)) as u32;
                 self.bar_used[config.reg_idx + 1] = true;
             }
         }
-- 
cgit 1.4.1