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authorColin Downs-Razouk <colindr@google.com>2020-04-30 15:48:47 -0700
committerCommit Bot <commit-bot@chromium.org>2020-05-18 23:56:23 +0000
commit43b1bc8f8ff7ff04b054374538ecad4a4525d283 (patch)
tree221f4deb7e88cf746f8af1c091660657ce48406f /devices/src/lib.rs
parent73665866a047c4602ab25ae6e20ce1f98f1f8e6e (diff)
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devices: irqchip: new irqchip module
This new module contains the irqchip trait and it's implementations. The
irqchips will work with the new hypervisor crate to abstract the
interaction between crosvm and kvm.

This just defines the irqchip trait and an empty implementation of the
KvmKernelIrqChip.

BUG=chromium:1077058
TEST=added test for creating a KvmKernelIrqChip and adding a Vcpu to it

Change-Id: Ic1609c965e0a057f5a9d4d74f1cae46edb46dcb4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/2197398
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Commit-Queue: Colin Downs-Razouk <colindr@google.com>
Diffstat (limited to 'devices/src/lib.rs')
-rw-r--r--devices/src/lib.rs2
1 files changed, 2 insertions, 0 deletions
diff --git a/devices/src/lib.rs b/devices/src/lib.rs
index 01c2b46..c945e00 100644
--- a/devices/src/lib.rs
+++ b/devices/src/lib.rs
@@ -8,6 +8,7 @@ mod bus;
 mod cmos;
 mod i8042;
 mod ioapic;
+mod irqchip;
 mod pci;
 mod pic;
 mod pit;
@@ -30,6 +31,7 @@ pub use self::bus::{Bus, BusDevice, BusRange, BusResumeDevice};
 pub use self::cmos::Cmos;
 pub use self::i8042::I8042Device;
 pub use self::ioapic::{Ioapic, IOAPIC_BASE_ADDRESS, IOAPIC_MEM_LENGTH_BYTES};
+pub use self::irqchip::*;
 pub use self::pci::{
     Ac97Backend, Ac97Dev, Ac97Parameters, PciAddress, PciConfigIo, PciConfigMmio, PciDevice,
     PciDeviceError, PciInterruptPin, PciRoot, VfioPciDevice,