edition: Eliminate blocks superseded by NLL

Before the new borrow checker in the 2018 edition, we sometimes used to
have to manually insert curly braced blocks to limit the scope of
borrows. These are no longer needed.

Details in:

https://doc.rust-lang.org/edition-guide/rust-2018/ownership-and-lifetimes/non-lexical-lifetimes.html

TEST=cargo check --all-features
TEST=local kokoro

Change-Id: I59f9f98dcc03c8790c53e080a527ad9b68c8d6f3
Reviewed-on: https://chromium-review.googlesource.com/1568075
Commit-Ready: David Tolnay <dtolnay@chromium.org>
Tested-by: David Tolnay <dtolnay@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>

17 files changed, 305 insertions, 361 deletions

diff --git a/crosvm_plugin/src/lib.rs b/crosvm_plugin/src/lib.rs
index 03315cb..31684b3 100644
--- a/crosvm_plugin/src/lib.rs
+++ b/crosvm_plugin/src/lib.rs
@@ -490,54 +490,51 @@ impl crosvm {
 
     fn reserve_range(&mut self, space: u32, start: u64, length: u64) -> result::Result<(), c_int> {
         let mut r = MainRequest::new();
-        {
-            let reserve: &mut MainRequest_ReserveRange = r.mut_reserve_range();
-            reserve.space = AddressSpace::from_i32(space as i32).ok_or(EINVAL)?;
-            reserve.start = start;
-            reserve.length = length;
-        }
+        let reserve: &mut MainRequest_ReserveRange = r.mut_reserve_range();
+        reserve.space = AddressSpace::from_i32(space as i32).ok_or(EINVAL)?;
+        reserve.start = start;
+        reserve.length = length;
+
         self.main_transaction(&r, &[])?;
         Ok(())
     }
 
     fn set_irq(&mut self, irq_id: u32, active: bool) -> result::Result<(), c_int> {
         let mut r = MainRequest::new();
-        {
-            let set_irq: &mut MainRequest_SetIrq = r.mut_set_irq();
-            set_irq.irq_id = irq_id;
-            set_irq.active = active;
-        }
+        let set_irq: &mut MainRequest_SetIrq = r.mut_set_irq();
+        set_irq.irq_id = irq_id;
+        set_irq.active = active;
+
         self.main_transaction(&r, &[])?;
         Ok(())
     }
 
     fn set_irq_routing(&mut self, routing: &[crosvm_irq_route]) -> result::Result<(), c_int> {
         let mut r = MainRequest::new();
-        {
-            let set_irq_routing: &mut RepeatedField<MainRequest_SetIrqRouting_Route> =
-                r.mut_set_irq_routing().mut_routes();
-            for route in routing {
-                let mut entry = MainRequest_SetIrqRouting_Route::new();
-                entry.irq_id = route.irq_id;
-                match route.kind {
-                    CROSVM_IRQ_ROUTE_IRQCHIP => {
-                        let irqchip: &mut MainRequest_SetIrqRouting_Route_Irqchip;
-                        irqchip = entry.mut_irqchip();
-                        // Safe because route.kind indicates which union field is valid.
-                        irqchip.irqchip = unsafe { route.route.irqchip }.irqchip;
-                        irqchip.pin = unsafe { route.route.irqchip }.pin;
-                    }
-                    CROSVM_IRQ_ROUTE_MSI => {
-                        let msi: &mut MainRequest_SetIrqRouting_Route_Msi = entry.mut_msi();
-                        // Safe because route.kind indicates which union field is valid.
-                        msi.address = unsafe { route.route.msi }.address;
-                        msi.data = unsafe { route.route.msi }.data;
-                    }
-                    _ => return Err(EINVAL),
+        let set_irq_routing: &mut RepeatedField<MainRequest_SetIrqRouting_Route> =
+            r.mut_set_irq_routing().mut_routes();
+        for route in routing {
+            let mut entry = MainRequest_SetIrqRouting_Route::new();
+            entry.irq_id = route.irq_id;
+            match route.kind {
+                CROSVM_IRQ_ROUTE_IRQCHIP => {
+                    let irqchip: &mut MainRequest_SetIrqRouting_Route_Irqchip;
+                    irqchip = entry.mut_irqchip();
+                    // Safe because route.kind indicates which union field is valid.
+                    irqchip.irqchip = unsafe { route.route.irqchip }.irqchip;
+                    irqchip.pin = unsafe { route.route.irqchip }.pin;
+                }
+                CROSVM_IRQ_ROUTE_MSI => {
+                    let msi: &mut MainRequest_SetIrqRouting_Route_Msi = entry.mut_msi();
+                    // Safe because route.kind indicates which union field is valid.
+                    msi.address = unsafe { route.route.msi }.address;
+                    msi.data = unsafe { route.route.msi }.data;
                 }
-                set_irq_routing.push(entry);
+                _ => return Err(EINVAL),
             }
+            set_irq_routing.push(entry);
         }
+
         self.main_transaction(&r, &[])?;
         Ok(())
     }
@@ -567,11 +564,10 @@ impl crosvm {
         new_state: &[u8],
     ) -> result::Result<(), c_int> {
         let mut r = MainRequest::new();
-        {
-            let set_state: &mut MainRequest_SetState = r.mut_set_state();
-            set_state.set = state_set;
-            set_state.state = new_state.to_vec();
-        }
+        let set_state: &mut MainRequest_SetState = r.mut_set_state();
+        set_state.set = state_set;
+        set_state.state = new_state.to_vec();
+
         self.main_transaction(&r, &[])?;
         Ok(())
     }
@@ -579,17 +575,16 @@ impl crosvm {
     fn set_identity_map_addr(&mut self, addr: u32) -> result::Result<(), c_int> {
         let mut r = MainRequest::new();
         r.mut_set_identity_map_addr().address = addr;
+
         self.main_transaction(&r, &[])?;
         Ok(())
     }
 
     fn pause_vcpus(&mut self, cpu_mask: u64, user: *mut c_void) -> result::Result<(), c_int> {
         let mut r = MainRequest::new();
-        {
-            let pause_vcpus: &mut MainRequest_PauseVcpus = r.mut_pause_vcpus();
-            pause_vcpus.cpu_mask = cpu_mask;
-            pause_vcpus.user = user as u64;
-        }
+        let pause_vcpus: &mut MainRequest_PauseVcpus = r.mut_pause_vcpus();
+        pause_vcpus.cpu_mask = cpu_mask;
+        pause_vcpus.user = user as u64;
         self.main_transaction(&r, &[])?;
         Ok(())
     }
@@ -713,16 +708,16 @@ impl crosvm_io_event {
         datamatch: u64,
     ) -> result::Result<crosvm_io_event, c_int> {
         let id = crosvm.get_id_allocator().alloc();
+
         let mut r = MainRequest::new();
-        {
-            let create: &mut MainRequest_Create = r.mut_create();
-            create.id = id;
-            let io_event: &mut MainRequest_Create_IoEvent = create.mut_io_event();
-            io_event.space = AddressSpace::from_i32(space as i32).ok_or(EINVAL)?;
-            io_event.address = addr;
-            io_event.length = length;
-            io_event.datamatch = datamatch;
-        }
+        let create: &mut MainRequest_Create = r.mut_create();
+        create.id = id;
+        let io_event: &mut MainRequest_Create_IoEvent = create.mut_io_event();
+        io_event.space = AddressSpace::from_i32(space as i32).ok_or(EINVAL)?;
+        io_event.address = addr;
+        io_event.length = length;
+        io_event.datamatch = datamatch;
+
         let ret = match crosvm.main_transaction(&r, &[]) {
             Ok((_, mut files)) => match files.pop() {
                 Some(evt) => return Ok(crosvm_io_event { id, evt }),
@@ -767,17 +762,17 @@ impl crosvm_memory {
             return Err(EINVAL);
         }
         let id = crosvm.get_id_allocator().alloc();
+
         let mut r = MainRequest::new();
-        {
-            let create: &mut MainRequest_Create = r.mut_create();
-            create.id = id;
-            let memory: &mut MainRequest_Create_Memory = create.mut_memory();
-            memory.offset = offset;
-            memory.start = start;
-            memory.length = length;
-            memory.read_only = read_only;
-            memory.dirty_log = dirty_log;
-        }
+        let create: &mut MainRequest_Create = r.mut_create();
+        create.id = id;
+        let memory: &mut MainRequest_Create_Memory = create.mut_memory();
+        memory.offset = offset;
+        memory.start = start;
+        memory.length = length;
+        memory.read_only = read_only;
+        memory.dirty_log = dirty_log;
+
         let ret = match crosvm.main_transaction(&r, &[fd]) {
             Ok(_) => return Ok(crosvm_memory { id, length }),
             Err(e) => e,
@@ -842,14 +837,14 @@ pub struct crosvm_irq_event {
 impl crosvm_irq_event {
     fn create(crosvm: &mut crosvm, irq_id: u32) -> result::Result<crosvm_irq_event, c_int> {
         let id = crosvm.get_id_allocator().alloc();
+
         let mut r = MainRequest::new();
-        {
-            let create: &mut MainRequest_Create = r.mut_create();
-            create.id = id;
-            let irq_event: &mut MainRequest_Create_IrqEvent = create.mut_irq_event();
-            irq_event.irq_id = irq_id;
-            irq_event.resample = true;
-        }
+        let create: &mut MainRequest_Create = r.mut_create();
+        create.id = id;
+        let irq_event: &mut MainRequest_Create_IrqEvent = create.mut_irq_event();
+        irq_event.irq_id = irq_id;
+        irq_event.resample = true;
+
         let ret = match crosvm.main_transaction(&r, &[]) {
             Ok((_, mut files)) => {
                 if files.len() >= 2 {
@@ -992,10 +987,9 @@ impl crosvm_vcpu {
 
     fn resume(&mut self) -> result::Result<(), c_int> {
         let mut r = VcpuRequest::new();
-        {
-            let resume: &mut VcpuRequest_Resume = r.mut_resume();
-            swap(&mut resume.data, &mut self.resume_data);
-        }
+        let resume: &mut VcpuRequest_Resume = r.mut_resume();
+        swap(&mut resume.data, &mut self.resume_data);
+
         self.vcpu_transaction(&r)?;
         Ok(())
     }
@@ -1025,11 +1019,10 @@ impl crosvm_vcpu {
         new_state: &[u8],
     ) -> result::Result<(), c_int> {
         let mut r = VcpuRequest::new();
-        {
-            let set_state: &mut VcpuRequest_SetState = r.mut_set_state();
-            set_state.set = state_set;
-            set_state.state = new_state.to_vec();
-        }
+        let set_state: &mut VcpuRequest_SetState = r.mut_set_state();
+        set_state.set = state_set;
+        set_state.state = new_state.to_vec();
+
         self.vcpu_transaction(&r)?;
         Ok(())
     }
@@ -1040,13 +1033,13 @@ impl crosvm_vcpu {
         msr_count: &mut usize,
     ) -> result::Result<(), c_int> {
         *msr_count = 0;
+
         let mut r = VcpuRequest::new();
-        {
-            let entry_indices: &mut Vec<u32> = r.mut_get_msrs().mut_entry_indices();
-            for entry in msr_entries.iter() {
-                entry_indices.push(entry.index);
-            }
+        let entry_indices: &mut Vec<u32> = r.mut_get_msrs().mut_entry_indices();
+        for entry in msr_entries.iter() {
+            entry_indices.push(entry.index);
         }
+
         let response = self.vcpu_transaction(&r)?;
         if !response.has_get_msrs() {
             return Err(EPROTO);
@@ -1064,28 +1057,26 @@ impl crosvm_vcpu {
 
     fn set_msrs(&mut self, msr_entries: &[kvm_msr_entry]) -> result::Result<(), c_int> {
         let mut r = VcpuRequest::new();
-        {
-            let set_msrs_entries: &mut RepeatedField<VcpuRequest_MsrEntry> =
-                r.mut_set_msrs().mut_entries();
-            for msr_entry in msr_entries.iter() {
-                let mut entry = VcpuRequest_MsrEntry::new();
-                entry.index = msr_entry.index;
-                entry.data = msr_entry.data;
-                set_msrs_entries.push(entry);
-            }
+        let set_msrs_entries: &mut RepeatedField<VcpuRequest_MsrEntry> =
+            r.mut_set_msrs().mut_entries();
+        for msr_entry in msr_entries.iter() {
+            let mut entry = VcpuRequest_MsrEntry::new();
+            entry.index = msr_entry.index;
+            entry.data = msr_entry.data;
+            set_msrs_entries.push(entry);
         }
+
         self.vcpu_transaction(&r)?;
         Ok(())
     }
 
     fn set_cpuid(&mut self, cpuid_entries: &[kvm_cpuid_entry2]) -> result::Result<(), c_int> {
         let mut r = VcpuRequest::new();
-        {
-            let set_cpuid_entries: &mut RepeatedField<CpuidEntry> = r.mut_set_cpuid().mut_entries();
-            for cpuid_entry in cpuid_entries.iter() {
-                set_cpuid_entries.push(cpuid_kvm_to_proto(cpuid_entry));
-            }
+        let set_cpuid_entries: &mut RepeatedField<CpuidEntry> = r.mut_set_cpuid().mut_entries();
+        for cpuid_entry in cpuid_entries.iter() {
+            set_cpuid_entries.push(cpuid_kvm_to_proto(cpuid_entry));
         }
+
         self.vcpu_transaction(&r)?;
         Ok(())
     }
diff --git a/data_model/src/lib.rs b/data_model/src/lib.rs
index 7d3fd46..8288c84 100644
--- a/data_model/src/lib.rs
+++ b/data_model/src/lib.rs
@@ -121,36 +121,30 @@ macro_rules! data_init_type {
             fn from_slice_alignment() {
                 let mut v = [0u8; 32];
                 $(
-                    let pre_len =  {
-                        let (pre, _, _) = unsafe { v.align_to::<$T>() };
-                        pre.len()
-                    };
-                    {
-                        let aligned_v = &mut v[pre_len..pre_len + size_of::<$T>()];
-                        {
-                            let from_aligned = $T::from_slice(aligned_v);
-                            assert_eq!(from_aligned, Some(&0));
-                        }
-                        {
-                            let from_aligned_mut = $T::from_mut_slice(aligned_v);
-                            assert_eq!(from_aligned_mut, Some(&mut 0));
-                        }
-                    }
+                    let (pre, _, _) = unsafe { v.align_to::<$T>() };
+                    let pre_len = pre.len();
+
+                    let aligned_v = &mut v[pre_len..pre_len + size_of::<$T>()];
+
+                    let from_aligned = $T::from_slice(aligned_v);
+                    assert_eq!(from_aligned, Some(&0));
+
+                    let from_aligned_mut = $T::from_mut_slice(aligned_v);
+                    assert_eq!(from_aligned_mut, Some(&mut 0));
+
                     for i in 1..size_of::<$T>() {
                         let begin = pre_len + i;
                         let end = begin + size_of::<$T>();
                         let unaligned_v = &mut v[begin..end];
-                        {
-                            let from_unaligned = $T::from_slice(unaligned_v);
-                            if align_of::<$T>() != 1 {
-                                assert_eq!(from_unaligned, None);
-                            }
+
+                        let from_unaligned = $T::from_slice(unaligned_v);
+                        if align_of::<$T>() != 1 {
+                            assert_eq!(from_unaligned, None);
                         }
-                        {
-                            let from_unaligned_mut = $T::from_mut_slice(unaligned_v);
-                            if align_of::<$T>() != 1 {
-                                assert_eq!(from_unaligned_mut, None);
-                            }
+
+                        let from_unaligned_mut = $T::from_mut_slice(unaligned_v);
+                        if align_of::<$T>() != 1 {
+                            assert_eq!(from_unaligned_mut, None);
                         }
                     }
                 )*
diff --git a/data_model/src/volatile_memory.rs b/data_model/src/volatile_memory.rs
index 27fe1ad..9bdc0f4 100644
--- a/data_model/src/volatile_memory.rs
+++ b/data_model/src/volatile_memory.rs
@@ -513,11 +513,9 @@ mod tests {
     #[test]
     fn ref_store() {
         let mut a = [0u8; 1];
-        {
-            let a_ref = &mut a[..];
-            let v_ref = a_ref.get_ref(0).unwrap();
-            v_ref.store(2u8);
-        }
+        let a_ref = &mut a[..];
+        let v_ref = a_ref.get_ref(0).unwrap();
+        v_ref.store(2u8);
         assert_eq!(a[0], 2);
     }
 
diff --git a/devices/src/ioapic.rs b/devices/src/ioapic.rs
index d8b3808..0e9c89b 100644
--- a/devices/src/ioapic.rs
+++ b/devices/src/ioapic.rs
@@ -261,27 +261,25 @@ impl Ioapic {
                     return;
                 }
 
-                {
-                    let entry = &mut self.redirect_table[index];
-                    if is_high_bits {
-                        entry.set(32, 32, val.into());
-                    } else {
-                        let before = *entry;
-                        entry.set(0, 32, val.into());
-
-                        // respect R/O bits.
-                        entry.set_delivery_status(before.get_delivery_status());
-                        entry.set_remote_irr(before.get_remote_irr());
-
-                        // Clear remote_irr when switching to edge_triggered.
-                        if entry.get_trigger_mode() == TriggerMode::Edge {
-                            entry.set_remote_irr(false);
-                        }
-
-                        // NOTE: on pre-4.0 kernels, there's a race we would need to work around.
-                        // "KVM: x86: ioapic: Fix level-triggered EOI and IOAPIC reconfigure race"
-                        // is the fix for this.
+                let entry = &mut self.redirect_table[index];
+                if is_high_bits {
+                    entry.set(32, 32, val.into());
+                } else {
+                    let before = *entry;
+                    entry.set(0, 32, val.into());
+
+                    // respect R/O bits.
+                    entry.set_delivery_status(before.get_delivery_status());
+                    entry.set_remote_irr(before.get_remote_irr());
+
+                    // Clear remote_irr when switching to edge_triggered.
+                    if entry.get_trigger_mode() == TriggerMode::Edge {
+                        entry.set_remote_irr(false);
                     }
+
+                    // NOTE: on pre-4.0 kernels, there's a race we would need to work around.
+                    // "KVM: x86: ioapic: Fix level-triggered EOI and IOAPIC reconfigure race"
+                    // is the fix for this.
                 }
 
                 // TODO(mutexlox): route MSI.
diff --git a/devices/src/pic.rs b/devices/src/pic.rs
index 33106ef..9b8235f 100644
--- a/devices/src/pic.rs
+++ b/devices/src/pic.rs
@@ -724,10 +724,8 @@ mod tests {
         // OCW2: Set rotate on auto EOI.
         data.pic.write(PIC_SECONDARY_COMMAND, &[0x80]);
 
-        {
-            let secondary_pic = &data.pic.pics[PicSelect::Secondary as usize];
-            assert!(secondary_pic.rotate_on_auto_eoi);
-        }
+        let secondary_pic = &data.pic.pics[PicSelect::Secondary as usize];
+        assert!(secondary_pic.rotate_on_auto_eoi);
 
         // OCW2: Clear rotate on auto EOI.
         data.pic.write(PIC_SECONDARY_COMMAND, &[0x00]);
diff --git a/devices/src/register_space/register.rs b/devices/src/register_space/register.rs
index 160412c..268b945 100644
--- a/devices/src/register_space/register.rs
+++ b/devices/src/register_space/register.rs
@@ -259,15 +259,13 @@ impl<T: RegisterValue> RegisterInterface for Register<T> {
         let total_size = (overlap.to - overlap.from) as usize + 1;
 
         let mut reg_value: T = self.lock().value;
-        {
-            let value: &mut [u8] = reg_value.as_mut_slice();
-            for i in 0..total_size {
-                value[my_start_idx + i] = self.apply_write_masks_to_byte(
-                    value[my_start_idx + i],
-                    data[write_start_idx + i],
-                    my_start_idx + i,
-                );
-            }
+        let value: &mut [u8] = reg_value.as_mut_slice();
+        for i in 0..total_size {
+            value[my_start_idx + i] = self.apply_write_masks_to_byte(
+                value[my_start_idx + i],
+                data[write_start_idx + i],
+                my_start_idx + i,
+            );
         }
 
         // A single u64 register is done by write to lower 32 bit and then higher 32 bit. Callback
diff --git a/devices/src/usb/xhci/event_ring.rs b/devices/src/usb/xhci/event_ring.rs
index 0b35ef7..4b510f1 100644
--- a/devices/src/usb/xhci/event_ring.rs
+++ b/devices/src/usb/xhci/event_ring.rs
@@ -89,20 +89,19 @@ impl EventRing {
         fence(Ordering::SeqCst);
 
         trb.set_cycle_bit(self.producer_cycle_state);
-        {
-            // Offset of cycle state byte.
-            const CYCLE_STATE_OFFSET: usize = 12usize;
-            let data = trb.as_slice();
-            // Trb contains 4 dwords, the last one contains cycle bit.
-            let cycle_bit_dword = &data[CYCLE_STATE_OFFSET..];
-            let address = self.enqueue_pointer;
-            let address = address
-                .checked_add(CYCLE_STATE_OFFSET as u64)
-                .ok_or(Error::BadEnqueuePointer(self.enqueue_pointer))?;
-            self.mem
-                .write_all_at_addr(cycle_bit_dword, address)
-                .map_err(Error::MemoryWrite)?;
-        }
+
+        // Offset of cycle state byte.
+        const CYCLE_STATE_OFFSET: usize = 12usize;
+        let data = trb.as_slice();
+        // Trb contains 4 dwords, the last one contains cycle bit.
+        let cycle_bit_dword = &data[CYCLE_STATE_OFFSET..];
+        let address = self.enqueue_pointer;
+        let address = address
+            .checked_add(CYCLE_STATE_OFFSET as u64)
+            .ok_or(Error::BadEnqueuePointer(self.enqueue_pointer))?;
+        self.mem
+            .write_all_at_addr(cycle_bit_dword, address)
+            .map_err(Error::MemoryWrite)?;
 
         usb_debug!(
             "event write to pointer {:#x}, trb_count {}, {}",
diff --git a/devices/src/usb/xhci/interrupter.rs b/devices/src/usb/xhci/interrupter.rs
index e850eb2..a896fb4 100644
--- a/devices/src/usb/xhci/interrupter.rs
+++ b/devices/src/usb/xhci/interrupter.rs
@@ -83,14 +83,12 @@ impl Interrupter {
     /// Send port status change trb for port.
     pub fn send_port_status_change_trb(&mut self, port_id: u8) -> Result<()> {
         let mut trb = Trb::new();
-        {
-            let psctrb = trb
-                .cast_mut::<PortStatusChangeEventTrb>()
-                .map_err(Error::CastTrb)?;
-            psctrb.set_port_id(port_id);
-            psctrb.set_completion_code(TrbCompletionCode::Success as u8);
-            psctrb.set_trb_type(TrbType::PortStatusChangeEvent as u8);
-        }
+        let psctrb = trb
+            .cast_mut::<PortStatusChangeEventTrb>()
+            .map_err(Error::CastTrb)?;
+        psctrb.set_port_id(port_id);
+        psctrb.set_completion_code(TrbCompletionCode::Success as u8);
+        psctrb.set_trb_type(TrbType::PortStatusChangeEvent as u8);
         self.add_event(trb)
     }
 
@@ -102,17 +100,15 @@ impl Interrupter {
         trb_addr: GuestAddress,
     ) -> Result<()> {
         let mut trb = Trb::new();
-        {
-            let ctrb = trb
-                .cast_mut::<CommandCompletionEventTrb>()
-                .map_err(Error::CastTrb)?;
-            ctrb.set_trb_pointer(trb_addr.0);
-            ctrb.set_command_completion_parameter(0);
-            ctrb.set_completion_code(completion_code as u8);
-            ctrb.set_trb_type(TrbType::CommandCompletionEvent as u8);
-            ctrb.set_vf_id(0);
-            ctrb.set_slot_id(slot_id);
-        }
+        let ctrb = trb
+            .cast_mut::<CommandCompletionEventTrb>()
+            .map_err(Error::CastTrb)?;
+        ctrb.set_trb_pointer(trb_addr.0);
+        ctrb.set_command_completion_parameter(0);
+        ctrb.set_completion_code(completion_code as u8);
+        ctrb.set_trb_type(TrbType::CommandCompletionEvent as u8);
+        ctrb.set_vf_id(0);
+        ctrb.set_slot_id(slot_id);
         self.add_event(trb)
     }
 
@@ -127,16 +123,14 @@ impl Interrupter {
         endpoint_id: u8,
     ) -> Result<()> {
         let mut trb = Trb::new();
-        {
-            let event_trb = trb.cast_mut::<TransferEventTrb>().map_err(Error::CastTrb)?;
-            event_trb.set_trb_pointer(trb_pointer);
-            event_trb.set_trb_transfer_length(transfer_length);
-            event_trb.set_completion_code(completion_code as u8);
-            event_trb.set_event_data(event_data.into());
-            event_trb.set_trb_type(TrbType::TransferEvent as u8);
-            event_trb.set_endpoint_id(endpoint_id);
-            event_trb.set_slot_id(slot_id);
-        }
+        let event_trb = trb.cast_mut::<TransferEventTrb>().map_err(Error::CastTrb)?;
+        event_trb.set_trb_pointer(trb_pointer);
+        event_trb.set_trb_transfer_length(transfer_length);
+        event_trb.set_completion_code(completion_code as u8);
+        event_trb.set_event_data(event_data.into());
+        event_trb.set_trb_type(TrbType::TransferEvent as u8);
+        event_trb.set_endpoint_id(endpoint_id);
+        event_trb.set_slot_id(slot_id);
         self.add_event(trb)
     }
 
diff --git a/devices/src/usb/xhci/scatter_gather_buffer.rs b/devices/src/usb/xhci/scatter_gather_buffer.rs
index c05afd5..da43b33 100644
--- a/devices/src/usb/xhci/scatter_gather_buffer.rs
+++ b/devices/src/usb/xhci/scatter_gather_buffer.rs
@@ -132,31 +132,29 @@ mod test {
     fn scatter_gather_buffer_test() {
         let gm = GuestMemory::new(&vec![(GuestAddress(0), 0x1000)]).unwrap();
         let mut td = TransferDescriptor::new();
+
         // In this td, we are going to have scatter buffer at 0x100, length 4, 0x200 length 2 and
         // 0x300 length 1.
+
         let mut trb = Trb::new();
-        {
-            let ntrb = trb.cast_mut::<NormalTrb>().unwrap();
-            ntrb.set_trb_type(TrbType::Normal as u8);
-            ntrb.set_data_buffer(0x100);
-            ntrb.set_trb_transfer_length(4);
-        }
+        let ntrb = trb.cast_mut::<NormalTrb>().unwrap();
+        ntrb.set_trb_type(TrbType::Normal as u8);
+        ntrb.set_data_buffer(0x100);
+        ntrb.set_trb_transfer_length(4);
         td.push(AddressedTrb { trb, gpa: 0 });
+
         let mut trb = Trb::new();
-        {
-            let ntrb = trb.cast_mut::<NormalTrb>().unwrap();
-            ntrb.set_trb_type(TrbType::Normal as u8);
-            ntrb.set_data_buffer(0x200);
-            ntrb.set_trb_transfer_length(2);
-        }
+        let ntrb = trb.cast_mut::<NormalTrb>().unwrap();
+        ntrb.set_trb_type(TrbType::Normal as u8);
+        ntrb.set_data_buffer(0x200);
+        ntrb.set_trb_transfer_length(2);
         td.push(AddressedTrb { trb, gpa: 0 });
+
         let mut trb = Trb::new();
-        {
-            let ntrb = trb.cast_mut::<NormalTrb>().unwrap();
-            ntrb.set_trb_type(TrbType::Normal as u8);
-            ntrb.set_data_buffer(0x300);
-            ntrb.set_trb_transfer_length(1);
-        }
+        let ntrb = trb.cast_mut::<NormalTrb>().unwrap();
+        ntrb.set_trb_type(TrbType::Normal as u8);
+        ntrb.set_data_buffer(0x300);
+        ntrb.set_trb_transfer_length(1);
         td.push(AddressedTrb { trb, gpa: 0 });
 
         let buffer = ScatterGatherBuffer::new(gm.clone(), td).unwrap();
diff --git a/devices/src/virtio/gpu/mod.rs b/devices/src/virtio/gpu/mod.rs
index 686c174..2c13acc 100644
--- a/devices/src/virtio/gpu/mod.rs
+++ b/devices/src/virtio/gpu/mod.rs
@@ -690,11 +690,9 @@ impl VirtioDevice for Gpu {
         let offset = offset as usize;
         let len = data.len();
         let mut cfg = self.get_config();
-        {
-            let cfg_slice = cfg.as_mut_slice();
-            if offset + len <= cfg_slice.len() {
-                cfg_slice[offset..offset + len].copy_from_slice(data);
-            }
+        let cfg_slice = cfg.as_mut_slice();
+        if offset + len <= cfg_slice.len() {
+            cfg_slice[offset..offset + len].copy_from_slice(data);
         }
         if (cfg.events_clear.to_native() & VIRTIO_GPU_EVENT_DISPLAY) != 0 {
             self.config_event = false;
diff --git a/kvm/src/lib.rs b/kvm/src/lib.rs
index dd8fd00..60ec2d1 100644
--- a/kvm/src/lib.rs
+++ b/kvm/src/lib.rs
@@ -956,25 +956,23 @@ impl Vm {
             vec_with_array_field::<kvm_irq_routing, kvm_irq_routing_entry>(routes.len());
         irq_routing[0].nr = routes.len() as u32;
 
-        {
-            // Safe because we ensured there is enough space in irq_routing to hold the number of
-            // route entries.
-            let irq_routes = unsafe { irq_routing[0].entries.as_mut_slice(routes.len()) };
-            for (route, irq_route) in routes.iter().zip(irq_routes.iter_mut()) {
-                irq_route.gsi = route.gsi;
-                match route.source {
-                    IrqSource::Irqchip { chip, pin } => {
-                        irq_route.type_ = KVM_IRQ_ROUTING_IRQCHIP;
-                        irq_route.u.irqchip = kvm_irq_routing_irqchip { irqchip: chip, pin }
-                    }
-                    IrqSource::Msi { address, data } => {
-                        irq_route.type_ = KVM_IRQ_ROUTING_MSI;
-                        irq_route.u.msi = kvm_irq_routing_msi {
-                            address_lo: address as u32,
-                            address_hi: (address >> 32) as u32,
-                            data,
-                            ..Default::default()
-                        }
+        // Safe because we ensured there is enough space in irq_routing to hold the number of
+        // route entries.
+        let irq_routes = unsafe { irq_routing[0].entries.as_mut_slice(routes.len()) };
+        for (route, irq_route) in routes.iter().zip(irq_routes.iter_mut()) {
+            irq_route.gsi = route.gsi;
+            match route.source {
+                IrqSource::Irqchip { chip, pin } => {
+                    irq_route.type_ = KVM_IRQ_ROUTING_IRQCHIP;
+                    irq_route.u.irqchip = kvm_irq_routing_irqchip { irqchip: chip, pin }
+                }
+                IrqSource::Msi { address, data } => {
+                    irq_route.type_ = KVM_IRQ_ROUTING_MSI;
+                    irq_route.u.msi = kvm_irq_routing_msi {
+                        address_lo: address as u32,
+                        address_hi: (address >> 32) as u32,
+                        data,
+                        ..Default::default()
                     }
                 }
             }
diff --git a/msg_socket/src/msg_on_socket.rs b/msg_socket/src/msg_on_socket.rs
index cf5e528..98976e8 100644
--- a/msg_socket/src/msg_on_socket.rs
+++ b/msg_socket/src/msg_on_socket.rs
@@ -212,13 +212,11 @@ rawfd_impl!(UnixDatagram);
 unsafe trait AlignedNew: Sized + DataInit {
     unsafe fn from_unaligned(buffer: &[u8]) -> Option<Self> {
         let mut value = std::mem::uninitialized::<Self>();
-        {
-            let value_mem = value.as_mut_slice();
-            if value_mem.len() != buffer.len() {
-                return None;
-            }
-            value_mem.copy_from_slice(buffer);
+        let value_mem = value.as_mut_slice();
+        if value_mem.len() != buffer.len() {
+            return None;
         }
+        value_mem.copy_from_slice(buffer);
         Some(value)
     }
 }
diff --git a/src/plugin/vcpu.rs b/src/plugin/vcpu.rs
index adbe7e1..1b65d43 100644
--- a/src/plugin/vcpu.rs
+++ b/src/plugin/vcpu.rs
@@ -343,17 +343,17 @@ impl PluginVcpu {
                 if offset >= len {
                     return false;
                 }
+
                 let mut wait_reason = VcpuResponse_Wait::new();
-                {
-                    let io = wait_reason.mut_io();
-                    io.space = match io_space {
-                        IoSpace::Ioport => AddressSpace::IOPORT,
-                        IoSpace::Mmio => AddressSpace::MMIO,
-                    };
-                    io.address = addr;
-                    io.is_write = data.is_write();
-                    io.data = data.as_slice().to_vec();
-                }
+                let io = wait_reason.mut_io();
+                io.space = match io_space {
+                    IoSpace::Ioport => AddressSpace::IOPORT,
+                    IoSpace::Mmio => AddressSpace::MMIO,
+                };
+                io.address = addr;
+                io.is_write = data.is_write();
+                io.data = data.as_slice().to_vec();
+
                 self.wait_reason.set(Some(wait_reason));
                 match self.handle_until_resume(vcpu) {
                     Ok(resume_data) => data.copy_from_slice(&resume_data),
@@ -478,21 +478,17 @@ impl PluginVcpu {
             response.mut_set_cpuid();
             let request_entries = &request.get_set_cpuid().entries;
             let mut cpuid = CpuId::new(request_entries.len());
-            {
-                let cpuid_entries = cpuid.mut_entries_slice();
-                for (request_entry, cpuid_entry) in
-                    request_entries.iter().zip(cpuid_entries.iter_mut())
-                {
-                    cpuid_entry.function = request_entry.function;
-                    if request_entry.has_index {
-                        cpuid_entry.index = request_entry.index;
-                        cpuid_entry.flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
-                    }
-                    cpuid_entry.eax = request_entry.eax;
-                    cpuid_entry.ebx = request_entry.ebx;
-                    cpuid_entry.ecx = request_entry.ecx;
-                    cpuid_entry.edx = request_entry.edx;
+            let cpuid_entries = cpuid.mut_entries_slice();
+            for (request_entry, cpuid_entry) in request_entries.iter().zip(cpuid_entries) {
+                cpuid_entry.function = request_entry.function;
+                if request_entry.has_index {
+                    cpuid_entry.index = request_entry.index;
+                    cpuid_entry.flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
                 }
+                cpuid_entry.eax = request_entry.eax;
+                cpuid_entry.ebx = request_entry.ebx;
+                cpuid_entry.ecx = request_entry.ecx;
+                cpuid_entry.edx = request_entry.edx;
             }
             vcpu.set_cpuid2(&cpuid)
         } else {
diff --git a/sys_util/src/handle_eintr.rs b/sys_util/src/handle_eintr.rs
index 670e8d2..d8cc0b3 100644
--- a/sys_util/src/handle_eintr.rs
+++ b/sys_util/src/handle_eintr.rs
@@ -184,76 +184,68 @@ mod tests {
     #[test]
     fn i32_eintr_rc() {
         let mut count = 3;
-        {
-            let mut dummy = || {
-                count -= 1;
-                if count > 0 {
-                    EINTR
-                } else {
-                    0
-                }
-            };
-            let res = handle_eintr_rc!(dummy());
-            assert_eq!(res, 0);
-        }
+        let mut dummy = || {
+            count -= 1;
+            if count > 0 {
+                EINTR
+            } else {
+                0
+            }
+        };
+        let res = handle_eintr_rc!(dummy());
+        assert_eq!(res, 0);
         assert_eq!(count, 0);
     }
 
     #[test]
     fn i32_eintr_errno() {
         let mut count = 3;
-        {
-            let mut dummy = || {
-                count -= 1;
-                if count > 0 {
-                    set_errno(EINTR);
-                    -1
-                } else {
-                    56
-                }
-            };
-            let res = handle_eintr_errno!(dummy());
-            assert_eq!(res, 56);
-        }
+        let mut dummy = || {
+            count -= 1;
+            if count > 0 {
+                set_errno(EINTR);
+                -1
+            } else {
+                56
+            }
+        };
+        let res = handle_eintr_errno!(dummy());
+        assert_eq!(res, 56);
         assert_eq!(count, 0);
     }
 
     #[test]
     fn sys_eintr() {
         let mut count = 7;
-        {
-            let mut dummy = || {
-                count -= 1;
-                if count > 1 {
-                    Err(SysError::new(EINTR))
-                } else {
-                    Ok(101)
-                }
-            };
-            let res = handle_eintr!(dummy());
-            assert_eq!(res, Ok(101));
-        }
+        let mut dummy = || {
+            count -= 1;
+            if count > 1 {
+                Err(SysError::new(EINTR))
+            } else {
+                Ok(101)
+            }
+        };
+        let res = handle_eintr!(dummy());
+        assert_eq!(res, Ok(101));
         assert_eq!(count, 1);
     }
 
     #[test]
     fn io_eintr() {
         let mut count = 108;
-        {
-            let mut dummy = || {
-                count -= 1;
-                if count > 99 {
-                    Err(io::Error::new(
-                        io::ErrorKind::Interrupted,
-                        "interrupted again :(",
-                    ))
-                } else {
-                    Ok(32)
-                }
-            };
-            let res = handle_eintr!(dummy());
-            assert_eq!(res.unwrap(), 32);
-        }
+        let mut dummy = || {
+            count -= 1;
+            if count > 99 {
+                Err(io::Error::new(
+                    io::ErrorKind::Interrupted,
+                    "interrupted again :(",
+                ))
+            } else {
+                Ok(32)
+            }
+        };
+        let res = handle_eintr!(dummy());
+        assert_eq!(res.unwrap(), 32);
         assert_eq!(count, 99);
     }
 }
diff --git a/sys_util/src/signalfd.rs b/sys_util/src/signalfd.rs
index 3c2b964..0b50ea4 100644
--- a/sys_util/src/signalfd.rs
+++ b/sys_util/src/signalfd.rs
@@ -152,6 +152,7 @@ mod tests {
 
     use crate::signal::SIGRTMIN;
     use libc::{pthread_sigmask, raise, sigismember, sigset_t};
+    use std::mem;
     use std::ptr::null;
 
     #[test]
@@ -175,17 +176,15 @@ mod tests {
     fn drop() {
         let sigid = SIGRTMIN() + 2;
 
-        // Put the SignalFd in a block where it will be dropped at the end.
-        #[allow(unused_variables)]
-        {
-            let sigrt_fd = SignalFd::new(sigid).unwrap();
-            unsafe {
-                let mut sigset: sigset_t = mem::zeroed();
-                pthread_sigmask(0, null(), &mut sigset as *mut sigset_t);
-                assert_eq!(sigismember(&sigset, sigid), 1);
-            }
+        let sigrt_fd = SignalFd::new(sigid).unwrap();
+        unsafe {
+            let mut sigset: sigset_t = mem::zeroed();
+            pthread_sigmask(0, null(), &mut sigset as *mut sigset_t);
+            assert_eq!(sigismember(&sigset, sigid), 1);
         }
 
+        mem::drop(sigrt_fd);
+
         // The signal should no longer be masked.
         unsafe {
             let mut sigset: sigset_t = mem::zeroed();
diff --git a/tests/plugins.rs b/tests/plugins.rs
index b00309f..ec094d1 100644
--- a/tests/plugins.rs
+++ b/tests/plugins.rs
@@ -67,12 +67,10 @@ fn build_plugin(src: &str) -> RemovePath {
         .stdin(Stdio::piped())
         .spawn()
         .expect("failed to spawn compiler");
-    {
-        let stdin = child.stdin.as_mut().expect("failed to open stdin");
-        stdin
-            .write_all(src.as_bytes())
-            .expect("failed to write source to stdin");
-    }
+    let stdin = child.stdin.as_mut().expect("failed to open stdin");
+    stdin
+        .write_all(src.as_bytes())
+        .expect("failed to write source to stdin");
 
     let status = child.wait().expect("failed to wait for compiler");
     assert!(status.success(), "failed to build plugin");
diff --git a/x86_64/src/cpuid.rs b/x86_64/src/cpuid.rs
index 1446d79..0a70a21 100644
--- a/x86_64/src/cpuid.rs
+++ b/x86_64/src/cpuid.rs
@@ -129,25 +129,22 @@ mod tests {
     fn feature_and_vendor_name() {
         let mut cpuid = kvm::CpuId::new(2);
 
-        {
-            let entries = cpuid.mut_entries_slice();
-            entries[0].function = 0;
-            entries[1].function = 1;
-            entries[1].ecx = 0x10;
-            entries[1].edx = 0;
-        }
+        let entries = cpuid.mut_entries_slice();
+        entries[0].function = 0;
+        entries[1].function = 1;
+        entries[1].ecx = 0x10;
+        entries[1].edx = 0;
         assert_eq!(Ok(()), filter_cpuid(1, 2, &mut cpuid));
-        {
-            let entries = cpuid.mut_entries_slice();
-            assert_eq!(entries[0].function, 0);
-            assert_eq!(1, (entries[1].ebx >> EBX_CPUID_SHIFT) & 0x000000ff);
-            assert_eq!(2, (entries[1].ebx >> EBX_CPU_COUNT_SHIFT) & 0x000000ff);
-            assert_eq!(
-                EBX_CLFLUSH_CACHELINE,
-                (entries[1].ebx >> EBX_CLFLUSH_SIZE_SHIFT) & 0x000000ff
-            );
-            assert_ne!(0, entries[1].ecx & (1 << ECX_HYPERVISOR_SHIFT));
-            assert_ne!(0, entries[1].edx & (1 << EDX_HTT_SHIFT));
-        }
+
+        let entries = cpuid.mut_entries_slice();
+        assert_eq!(entries[0].function, 0);
+        assert_eq!(1, (entries[1].ebx >> EBX_CPUID_SHIFT) & 0x000000ff);
+        assert_eq!(2, (entries[1].ebx >> EBX_CPU_COUNT_SHIFT) & 0x000000ff);
+        assert_eq!(
+            EBX_CLFLUSH_CACHELINE,
+            (entries[1].ebx >> EBX_CLFLUSH_SIZE_SHIFT) & 0x000000ff
+        );
+        assert_ne!(0, entries[1].ecx & (1 << ECX_HYPERVISOR_SHIFT));
+        assert_ne!(0, entries[1].edx & (1 << EDX_HTT_SHIFT));
     }
 }