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authorWill Dietz <w@wdtz.org>2022-05-29 12:19:51 -0500
committerGitHub <noreply@github.com>2022-05-29 12:19:51 -0500
commitbc6116b23f35120b352659fafe1ece9916b92ecf (patch)
treefabd11b16158aaedd0860b33507bb8adcb286a9e
parentb571ef8fcbb301615fdc1b2ea404e74af7cf0444 (diff)
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firrtl: init at 1.5.3 (#171065)
-rw-r--r--pkgs/development/compilers/firrtl/default.nix60
-rw-r--r--pkgs/top-level/all-packages.nix2
2 files changed, 62 insertions, 0 deletions
diff --git a/pkgs/development/compilers/firrtl/default.nix b/pkgs/development/compilers/firrtl/default.nix
new file mode 100644
index 00000000000..5a59060b6f2
--- /dev/null
+++ b/pkgs/development/compilers/firrtl/default.nix
@@ -0,0 +1,60 @@
+{ lib, stdenv, jre, setJavaClassPath, coursier, makeWrapper }:
+
+stdenv.mkDerivation rec {
+  pname = "firrtl";
+  version = "1.5.3";
+  scalaVersion = "2.13"; # pin, for determinism
+
+  deps = stdenv.mkDerivation {
+    pname = "${pname}-deps";
+    inherit version;
+    nativeBuildInputs = [ coursier ];
+    buildCommand = ''
+      export COURSIER_CACHE=$(pwd)
+      cs fetch edu.berkeley.cs:${pname}_${scalaVersion}:${version} > deps
+      mkdir -p $out/share/java
+      cp $(< deps) $out/share/java
+    '';
+    outputHashMode = "recursive";
+    outputHash = "sha256-xy3zdJZk6Q2HbEn5tRQ9Z0AjyXEteXepoWDaATjiUUw=";
+  };
+
+  nativeBuildInputs = [ makeWrapper setJavaClassPath ];
+  buildInputs = [ deps ];
+
+  dontUnpack = true;
+
+  installPhase = ''
+    runHook preInstall
+
+    makeWrapper ${jre}/bin/java $out/bin/${pname} \
+      --add-flags "-cp $CLASSPATH firrtl.stage.FirrtlMain"
+
+    runHook postInstall
+  '';
+
+  doInstallCheck = true;
+  installCheckPhase = ''
+    $out/bin/firrtl --firrtl-source "${''
+        circuit test:
+          module test:
+            input a: UInt<8>
+            input b: UInt<8>
+            output o: UInt
+            o <= add(a, not(b))
+      ''}" -o test.v
+    cat test.v
+    grep -qFe "module test" -e "endmodule" test.v
+  '';
+
+  meta = with lib; {
+    description = "Flexible Intermediate Representation for RTL";
+    longDescription = ''
+      Firrtl is an intermediate representation (IR) for digital circuits
+      designed as a platform for writing circuit-level transformations.
+    '';
+    homepage = "https://www.chisel-lang.org/firrtl/";
+    license = licenses.asl20;
+    maintainers =  with maintainers; [ dtzWill ];
+  };
+}
diff --git a/pkgs/top-level/all-packages.nix b/pkgs/top-level/all-packages.nix
index 1137f848960..5fb42d1321f 100644
--- a/pkgs/top-level/all-packages.nix
+++ b/pkgs/top-level/all-packages.nix
@@ -12496,6 +12496,8 @@ with pkgs;
 
   fennel = callPackage ../development/compilers/fennel { };
 
+  firrtl = callPackage ../development/compilers/firrtl { };
+
   flasm = callPackage ../development/compilers/flasm { };
 
   flyctl = callPackage ../development/web/flyctl { };