Add common types and constants for split IRQ chip.

These will come in handy for reducing code duplication and simplifying
PIC/IOAPIC/PIT/interrupt routing code.

TEST=Built
BUG=chromium:908689

Change-Id: I696e9f51231a8e39640f1fd0af055b48048bc134
Reviewed-on: https://chromium-review.googlesource.com/1518557
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Miriam Zimmerman <mutexlox@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: David Tolnay <dtolnay@chromium.org>

4 files changed, 77 insertions, 0 deletions

diff --git a/Cargo.lock b/Cargo.lock
index adda55b..62cc52f 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -530,6 +530,7 @@ name = "x86_64"
 version = "0.1.0"
 dependencies = [
  "arch 0.1.0",
+ "bit_field 0.1.0",
  "byteorder 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "cc 1.0.25 (registry+https://github.com/rust-lang/crates.io-index)",
  "data_model 0.1.0",
diff --git a/x86_64/Cargo.toml b/x86_64/Cargo.toml
index 521573b..47a281c 100644
--- a/x86_64/Cargo.toml
+++ b/x86_64/Cargo.toml
@@ -6,6 +6,7 @@ build = "build.rs"
 
 [dependencies]
 arch = { path = "../arch" }
+bit_field = { path = "../bit_field" }
 data_model = { path = "../data_model" }
 devices = { path = "../devices" }
 io_jail = { path = "../io_jail" }
diff --git a/x86_64/src/lib.rs b/x86_64/src/lib.rs
index 0038a25..e200569 100644
--- a/x86_64/src/lib.rs
+++ b/x86_64/src/lib.rs
@@ -3,6 +3,7 @@
 // found in the LICENSE file.
 
 extern crate arch;
+extern crate bit_field;
 extern crate byteorder;
 extern crate data_model;
 extern crate devices;
@@ -65,7 +66,9 @@ mod gdt;
 mod interrupts;
 mod mptable;
 mod regs;
+mod split_irqchip_common;
 
+pub use self::split_irqchip_common::*;
 use std::error::Error as StdError;
 use std::ffi::{CStr, CString};
 use std::fmt::{self, Display};
diff --git a/x86_64/src/split_irqchip_common.rs b/x86_64/src/split_irqchip_common.rs
new file mode 100644
index 0000000..f43ab69
--- /dev/null
+++ b/x86_64/src/split_irqchip_common.rs
@@ -0,0 +1,72 @@
+// Copyright 2019 The Chromium OS Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+
+// Common constants and types used for Split IRQ chip devices (e.g. PIC, PIT, IOAPIC).
+
+use bit_field::*;
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum DestinationMode {
+    Physical = 0,
+    Logical = 1,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum TriggerMode {
+    Edge = 0,
+    Level = 1,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum DeliveryMode {
+    DeliveryModeFixed = 0b000,
+    DeliveryModeLowest = 0b001,
+    DeliveryModeSMI = 0b010,        // System management interrupt
+    DeliveryModeRemoteRead = 0b011, // This is no longer supported by intel.
+    DeliveryModeNMI = 0b100,        // Non maskable interrupt
+    DeliveryModeInit = 0b101,
+    DeliveryModeStartup = 0b110,
+    DeliveryModeExternal = 0b111,
+}
+
+#[bitfield]
+#[derive(Clone, Copy, PartialEq)]
+pub struct MsiAddressMessageNonRemappable {
+    reserved: BitField2,
+    destination_mode: BitField1,
+    redirection_hint: BitField1,
+    reserved_2: BitField8,
+    destination_id: BitField8,
+    // According to Intel's implementation of MSI, these bits must always be 0xfee.
+    always_0xfee: BitField12,
+}
+
+#[bitfield]
+#[derive(Clone, Copy, PartialEq)]
+pub struct MsiAddressMessageRemappable {
+    reserved: BitField2,
+    handle_hi: BitField1, // Bit 15 of handle
+    shv: BitField1,
+    interrupt_format: BitField1,
+    handle_low: BitField15, // Bits 0-14 of handle.
+    // According to Intel's implementation of MSI, these bits must always be 0xfee.
+    always_0xfee: BitField12,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum MsiAddressMessage {
+    NonRemappable(MsiAddressMessageNonRemappable),
+    Remappable(MsiAddressMessageRemappable),
+}
+
+#[bitfield]
+#[derive(Clone, Copy, PartialEq)]
+struct MsiDataMessage {
+    vector: BitField8,
+    delivery_mode: BitField3,
+    reserved: BitField3,
+    level: BitField1,
+    trigger: BitField1,
+    reserved2: BitField16,
+}