diff options
Diffstat (limited to 'pkgs/development/compilers/llvm/5/fix-gcc9.patch')
-rw-r--r-- | pkgs/development/compilers/llvm/5/fix-gcc9.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/pkgs/development/compilers/llvm/5/fix-gcc9.patch b/pkgs/development/compilers/llvm/5/fix-gcc9.patch new file mode 100644 index 00000000000..eaf71f1468d --- /dev/null +++ b/pkgs/development/compilers/llvm/5/fix-gcc9.patch @@ -0,0 +1,33 @@ +diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp +index f79cb0e6..c6279046 100644 +--- a/lib/Target/Mips/MipsFastISel.cpp ++++ b/lib/Target/Mips/MipsFastISel.cpp +@@ -70,6 +70,7 @@ + #include <cassert> + #include <cstdint> + #include <new> ++#include <array> + + #define DEBUG_TYPE "mips-fastisel" + +@@ -1309,13 +1310,13 @@ bool MipsFastISel::fastLowerArguments() { + return false; + } + +- const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2, +- Mips::A3}; +- const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14}; +- const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7}; +- ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin(); +- ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin(); +- ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin(); ++ std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2, ++ Mips::A3}}; ++ std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}}; ++ std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}}; ++ auto NextGPR32 = GPR32ArgRegs.begin(); ++ auto NextFGR32 = FGR32ArgRegs.begin(); ++ auto NextAFGR64 = AFGR64ArgRegs.begin(); + + struct AllocatedReg { + const TargetRegisterClass *RC; |