1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
// Copyright 2018 The Chromium OS Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
//! Implements pci devices and busses.
mod ac97;
mod ac97_bus_master;
mod ac97_mixer;
mod ac97_regs;
mod msix;
mod pci_configuration;
mod pci_device;
mod pci_root;
mod vfio_pci;
pub use self::ac97::Ac97Dev;
pub use self::msix::MsixCap;
pub use self::pci_configuration::{
PciBarConfiguration, PciBarPrefetchable, PciBarRegionType, PciCapability, PciCapabilityID,
PciClassCode, PciConfiguration, PciHeaderType, PciProgrammingInterface, PciSerialBusSubClass,
PciSubclass,
};
pub use self::pci_device::Error as PciDeviceError;
pub use self::pci_device::PciDevice;
pub use self::pci_root::{PciConfigIo, PciConfigMmio, PciRoot};
pub use self::vfio_pci::VfioPciDevice;
/// PCI has four interrupt pins A->D.
#[derive(Copy, Clone)]
pub enum PciInterruptPin {
IntA,
IntB,
IntC,
IntD,
}
impl PciInterruptPin {
pub fn to_mask(self) -> u32 {
self as u32
}
}
|