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path: root/devices/src/pci
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* devices: pci: replace byteorder with from_le_bytes()Daniel Verkamp2019-08-26
| | | | | | | | | | | | | | Use the standardized from_le_bytes() functions rather than the byteorder crate. BUG=None TEST=./build_test Change-Id: I07a062bf63c5d3ae1e25f403713bf9a1677e8cba Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1761155 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Zach Reizner <zachr@chromium.org>
* ac97: remove duplicated codeFletcher Woodruff2019-08-20
| | | | | | | | | | | | | | | | Crosvm's AC97 device had code that was duplicated between playback and capture stream creation. Abstract that code out so it can be shared. BUG=chromium:968724 TEST=aplay /dev/urandom within container Change-Id: If2fb50a0655656726dd9c6255bc84493e91c04e3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1749948 Tested-by: Fletcher Woodruff <fletcherw@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chih-Yang Hsia <paulhsia@chromium.org> Reviewed-by: Dylan Reid <dgreid@chromium.org> Commit-Queue: Fletcher Woodruff <fletcherw@chromium.org>
* ac97: Fix device real time priority issuepaulhsia2019-08-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Add allow sched_setscheduler call in seccomp policy - Change the real time priority constant AUDIO_THREAD_RTPRIO to 10 to match all other clients' priority. Run the following commands to test 1. ulimit -r 10 2. crosvm run -r ./vm_rootfs.img -c 1 -m 1024 -s /run --cid 5 --host_ip \ 100.115.92.25 --netmask 255.255.255.252 --cras-audio \ --params="snd_intel8x0.inside_vm=1 snd_intel8x0.ac97_clock=48000" \ --mac d2:47:f7:c5:9e:53 ./vm_kernel 3. aplay -Dhw:0,0 -f dat /dev/zero 4. ps -AT -o comm,rtprio | grep crosvm should see a thread running with rtprio=10 BUG=chromium:983533 BUG=b:138262556 TEST=Test with eve (x86_64) and bob (arm) Change-Id: Idc3711d03d716741f7cefd9a89b14ae4c20c2033 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1729089 Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Chih-Yang Hsia <paulhsia@chromium.org> Reviewed-by: Dylan Reid <dgreid@chromium.org> Commit-Queue: Chih-Yang Hsia <paulhsia@chromium.org>
* tree-wide: update to new inclusive range syntaxDylan Reid2019-07-24
| | | | | | | | | | | 1.38 nightly started warning about using `...` vs `..=`, update to avoid the warning. Signed-off-by: Dylan Reid <dgreid@chromium.org> Change-Id: Ibc3d24c5410b6eed9a1207db21e529ec6a763376 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1715575 Reviewed-by: Zach Reizner <zachr@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com>
* devices: silence unused code warning in PCIDaniel Verkamp2019-07-10
| | | | | | | | | | | | | | | | Now that nothing uses the PCI-to-PCI bridge device type, the compiler warns that it is never constructed. Mark the PciHeaderType enum to allow this, since the enum is public and could be constructed outside this file. BUG=None TEST=./build_test Change-Id: I6832996c4e00a33cc1ba88d97fede65b226cbfc5 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1691239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* pci: Let device could trap pci config read/writeXiong Zhang2019-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently device impliments PciDevice trait, it will return config register to bus trait at pci cfg r/w, then BusDevice trait on behave of device to do actual pci config r/w. But vfio device need to handle the pci config r/w by itself, as vfio device need to transfer this request to kernel. For pci config read, this patch delete PciDevice->config_registers(), and add PciDevice->read_config_register(), then BusDevice-> config_register_read() call PciDevice->read_config_register(), finally Device could trap the PciConfig Read. For pci config write, it is similiar with pci config read. But the common code is moved into PciConfiguration. BUG=none TEST=none Change-Id: Ie6bd3a8c94f523d6fb1ef3d1e97d087bb0407d9f Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1580457 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
* devices: pci: preserve read-only bits in write_regDaniel Verkamp2019-06-25
| | | | | | | | | | | | | | | | | | The 32-bit write_reg() function for PCI configuration space masked off non-writable (read-only) bits from the incoming value, but it did not preserve the original bits from the register; this results in writes to read-only registers to clear all read-only bits to 0 instead. Preserve the original value of the read-only bits and add a test to verify that this works. BUG=None TEST=./build_test Change-Id: Icc67b429f17d519ec4e9090f8e0ce48aaff76491 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1660204 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: check BAR address alignmentDaniel Verkamp2019-06-25
| | | | | | | | | | | | | | | Each PCI BAR address must be aligned to at least its own size to allow the BAR sizing mechanism to work properly. Add a check in add_pci_bar() to enforce this. BUG=None TEST=Boot vm_kernel in crosvm Change-Id: Iee9d866c4982bd79935337682bd50b9205b95024 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1660203 Reviewed-by: Dylan Reid <dgreid@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com>
* devices: pci: allocate BARs with correct alignmentDaniel Verkamp2019-06-25
| | | | | | | | | | | | | | | | | | Each PCI BAR must be aligned to at least its own size to allow the BAR sizing mechanism to work. Change all BAR allocations to use allocate_with_align(), specifying the size as the alignment. In particular, this fixes the alignment of the XHCI BAR, whose size is larger than a page (the default MMIO allocator alignment). BUG=None TEST=Boot vm_kernel in crosvm Change-Id: Icba03771a896b9b4feae608efdb7685fe24f8b98 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1660202 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: Change host brige into IntelXiong Zhang2019-06-25
| | | | | | | | | | | | | | | | For kvmgt linux guest, intel graphic driver i915 need intel host bridge located at 0000:00.0, so this patch change the vendor id of 0000:00.0 device to intel. BUG=none TEST=none Change-Id: I52f2341d25859f2b7d4a3837f4f0c8a4b2443525 Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com> Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1581139 Reviewed-by: Dylan Reid <dgreid@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com>
* devices: pci: use header type 0 for host bridgeDaniel Verkamp2019-06-25
| | | | | | | | | | | | | | | | | | | Previously, we were using header type 1 (which is meant to be used only for PCI-to-PCI bridges), which upsets the Linux PCI probing code: pci 0000:00:00.0: ignoring class 0x060000 (doesn't match header type 01) Switch to the standard type 0 header instead, which makes the kernel happy and matches what real hardware uses. BUG=None TEST=Boot vm_kernel (Linux 4.19) in crosvm Change-Id: I33d10bda39edf6d949827963cebbfe66c9147ea2 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1660892 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* eliminate mut from non-mut referencesZach Reizner2019-06-04
| | | | | | | | | | | | | | | | | | | | | | | This manifested itself in a couple places that were turning shared memory buffers into slices for the purposes of passing these slices to `Read` and `Write` trait methods. However, this required the removal of the methods that took `Read` and `Write` instances. This was a convenient interface but impossible to implement safely because making slices from raw pointers without enforcing safety guarantees causes undefined behaviour in Rust. It turns out lots of code in crosvm was using these interfaces indirectly, which explains why this CL touches so much. TEST=crosvm run BUG=chromium:938767 Change-Id: I4ff40c98da6ed08a4a42f4c31f0717f81b1c5863 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1636685 Reviewed-by: Zach Reizner <zachr@chromium.org> Tested-by: Zach Reizner <zachr@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Zach Reizner <zachr@chromium.org>
* devices: Add capture path in AC'97 PCI devicepaulhsia2019-04-20
| | | | | | | | | | | | | | | | | Add capture support in AC'97 PCI device. Only capture at 48kHz is supported. BUG=chromium:932268 TEST=cargo test -p device start_capture TEST=Run crosvm with `--cras-audio` option to run a guest vm then test audio capture by command $ arecord -D hw:0,0 -r 48000 -f dat -c 2 /tmp/test.raw Change-Id: Ie3aab1004695f0df607fef8fc337fa58cb723b65 Reviewed-on: https://chromium-review.googlesource.com/1573600 Commit-Ready: Chih-Yang Hsia <paulhsia@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* resources+pci: allocator rework (allocation tags)Daniel Prilik2019-04-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | AddressAllocator now maintains a HashMap<Alloc, (u64, u64, u64)>, which uniquely maps a Allocation enum (e.g: PciBar(bus, dev, bar), GpuRenderNode, etc...) to it's address, size, and human-readable tag / description. The interface has also been modified to use Error instead of Option. Aside from improving debugging, tracking allocations will have numerous uses in the future. For example, when allocating guest memory over VmControl sockets, it will be possible to restrict allocations to pre-allocated slices of memory owned by the requesting device. To plumb through PCI information to PCI devices, this CL necessitated the addition of a PciDevice method called `assign_bus_dev`, which notifies PCI devices of their uniquely assigned Bus and Device numbers. BUG=chromium:936567 TEST=cargo test -p resources && cargo build --features="gpu gpu-forward" Change-Id: I8b4b0e32c6f3168138739249ede53d03143ee5c3 Reviewed-on: https://chromium-review.googlesource.com/1536207 Commit-Ready: Daniel Prilik <prilik@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Zach Reizner <zachr@chromium.org>
* resources: add build method to SystemAllocatorDaniel Prilik2019-04-17
| | | | | | | | | | | | | | | | | | AddressRanges' name doesn't suggest that it's a SystemAllocator builder. This CL renames it to SystemAllocatorBuilder, and adds a SystemAllocator::builder() that removes the need to have a separate import for the Builder. A minor change, but it cleans up the interface a bit. BUG=chromium:936567 TEST=cargo test -p resources && cargo build Change-Id: I6d14368490c0d3c4018858f541e4ae5390995878 Reviewed-on: https://chromium-review.googlesource.com/1540398 Commit-Ready: Daniel Prilik <prilik@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Zach Reizner <zachr@chromium.org>
* clippy: Resolve useless_formatDavid Tolnay2019-04-17
| | | | | | | | | | | TEST=bin/clippy Change-Id: I13fcde5655f9f9c207c9a704fa32b99510946a1e Reviewed-on: https://chromium-review.googlesource.com/1566893 Commit-Ready: David Tolnay <dtolnay@chromium.org> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* edition: Fill in macro importsDavid Tolnay2019-04-15
| | | | | | | | | | | | | | | | | | | | Macros were previously imported through `#[macro_use] extern crate`, which is basically a glob import of all macros from the crate. As of 2018 edition of Rust, `extern crate` is no longer required and macros are imported individually like any other item from a dependency. This CL fills in all the appropriate macro imports that will allow us to remove our use of `extern crate` in a subsequent CL. TEST=cargo check --all-features --tests TEST=kokoro Change-Id: If2ec08b06b743abf5f62677c6a9927c3d5d90a54 Reviewed-on: https://chromium-review.googlesource.com/1565546 Commit-Ready: David Tolnay <dtolnay@chromium.org> Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
* edition: Use 2018-style paths in devices crateDavid Tolnay2019-04-09
| | | | | | | | | | | | | | | | These are import paths in new code added since CL:1513054 that need to be made compatible with 2018 edition's treatment of paths. TEST=cargo check TEST=cargo check --all-features TEST=cargo check --target aarch64-unknown-linux-gnu Change-Id: Icb3ecf2fb2015332e0c03cdc22bff2ecab2c40df Reviewed-on: https://chromium-review.googlesource.com/1559264 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
* edition: Use dyn syntax for trait objectsDavid Tolnay2019-04-08
| | | | | | | | | | | | | | | | | | | | | Found by running: `cargo rustc -- -D bare_trait_objects` Bare trait objects like `&Trait` and `Box<Trait>` are soft-deprecated in 2018 edition and will start warning at some point. As part of this, I replaced `Box<Trait + 'static>` with `Box<dyn Trait>` because the 'static bound is implied for boxed trait objects. TEST=cargo check --all-features TEST=cargo check --target aarch64-unknown-linux-gnu TEST=local kokoro Change-Id: I41c4f13530bece8a34a8ed1c1afd7035b8f86f19 Reviewed-on: https://chromium-review.googlesource.com/1513059 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
* pci: match pci cap structs with linux/virtio_pci.hDaniel Prilik2019-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VirtioPciCap omits the `cap_vndr` and `cap_next` fields from it's definition, deferring the instantiation of these bytes to the add_capability method in PCI configuration. There is even a comment on add_capability that mentions this omission. Unfortunately, comments tend not to be read, and mismatches between the linux headers and crosvm structures can result in some subtle and tricky to debug bugs, especially when implementing other types of virtio capabilties that subsume VirtioPciCap. Case in point, when implementing the VirtioPciShmCap (used by virtio-fs), this subtle mismatch resulted in a bug where an additional 2 bytes of padding were inserted between the `cap` member and the `offset_hi` member (see CL:1493014 for the exact struct). Since the cap_len field was instantiated using mem::sizeof Self, the additional padding just-so-happened to be the perfect ammount to sneak past the sanity checks in add_capabilities. The bug manifested itself by shifting over the length_hi field by 16 bits, resulting in much larger than expected cache sizes. This CL brings the VirtioPciCap structures in-line with their linux/virtio_pci.h counterparts, marking the structures as repr(C) (as opposed to repr(packed)) and leaving the cap_vndr and cap_next members in the struct, noting that they will be automatically populated in add_capability. BUG=chromium:936567 TEST=cargo test -p devices, boot vm Change-Id: Ia360e532b58070372a52346e85dd4e30e81ace7a Reviewed-on: https://chromium-review.googlesource.com/1540397 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* implement xhci and add it to pci busJingkui Wang2019-03-17
| | | | | | | | | | | | | | Implement xhci controller, setup seccomp filters and add xhci to pci bus. CQ-DEPEND=CL:1512761 BUG=chromium:831850 TEST=local build Change-Id: I5c05452ece66e99d3a670e259e095fca616e835d Reviewed-on: https://chromium-review.googlesource.com/1512762 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Jingkui Wang <jkwang@google.com> Reviewed-by: Jingkui Wang <jkwang@google.com>
* edition: Update absolute paths to 2018 styleDavid Tolnay2019-03-13
| | | | | | | | | | | | | | | | | | | | | | | | | | This is an easy step toward adopting 2018 edition eventually, and will make any future CL that sets `edition = "2018"` this much smaller. The module system changes in Rust 2018 are described here: https://doc.rust-lang.org/edition-guide/rust-2018/module-system/path-clarity.html Generated by running: cargo fix --edition --all in each workspace, followed by bin/fmt. TEST=cargo check TEST=cargo check --all-features TEST=cargo check --target aarch64-unknown-linux-gnu Change-Id: I000ab5e69d69aa222c272fae899464bbaf65f6d8 Reviewed-on: https://chromium-review.googlesource.com/1513054 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
* devices: PCI: add capabilities callbackDaniel Prilik2019-03-11
| | | | | | | | | | | | | virtio devices should be able to specify capabilities BUG=chromium:936567 TEST=boot vm Change-Id: I049f9967eb59a7904528fff5aea844e30c636e28 Reviewed-on: https://chromium-review.googlesource.com/1493012 Commit-Ready: Daniel Prilik <prilik@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Stephen Barber <smbarber@chromium.org>
* devices: PCI: fix underflow for 64 bit BAR configDaniel Prilik2019-03-08
| | | | | | | | | | | | | | | underflow occurs when configuring a 64 bit register with a <33 bit address. BUG=chromium:924405 TEST=boot VM Change-Id: I53a309b7bff3c91012bacb12d9fc9f8ceed68699 Reviewed-on: https://chromium-review.googlesource.com/1493011 Commit-Ready: Daniel Prilik <prilik@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-by: Zach Reizner <zachr@chromium.org>
* PCI: Return results from pci setup functionsDylan Reid2019-03-06
| | | | | | | | | | | | | | | | Enough failure cases have been added to `add_pci_bar` and `add_pci_capabilities` that they should return unique errors instead of an `Option`. BUG=none TEST=cargo test in devices Signed-off-by: Dylan Reid <dgreid@chromium.org> Change-Id: Ice2a06d2944011f95707f113f9d709da15c90cfe Reviewed-on: https://chromium-review.googlesource.com/1497740 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* ac97: Add top level unit testDylan Reid2019-03-04
| | | | | | | | | | | Check that the device can be created. This test would have caught the bug with adding pci bars. Change-Id: Ib0cc2edf0d8d1b2d95d9c3588ac325b5da886603 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1497738 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
* error: Consistently use Display instead of error description()David Tolnay2019-03-02
| | | | | | | | | | | | | | | | The description method is deprecated and its signature forces less helpful error messages than what Display can provide. BUG=none TEST=cargo check --all-features TEST=cargo check --target aarch64-unknown-linux-gnu Change-Id: I27fc99d59d0ef457c5273dc53e4c563ef439c2c0 Reviewed-on: https://chromium-review.googlesource.com/1497735 Commit-Ready: David Tolnay <dtolnay@chromium.org> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* ac97: Fix setting the pci configDylan Reid2019-03-02
| | | | | | | | | | | | | When switching to PciBarConfiguration, the set_* functions were changed to return self. The self for register index 1 was not being used. TEST=boot a VM and check that there isn't a pci bus creation error. Change-Id: I8d5162c70fcec1159a6283e26e744d0c3c76b804 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1497737 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Chirantan Ekbote <chirantan@chromium.org>
* devices: PCI: use configuration callbackGurchetan Singh2019-03-01
| | | | | | | | | | | | | | | Not sure if adding the device addresses to the mmio bus is the desired behavior, but it seems to work. BUG=chromium:924405 TEST=boot VM Change-Id: I7f6057b3e7d041a52b251af1203353ba7a0d3c22 Reviewed-on: https://chromium-review.googlesource.com/1480743 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* devices: use PCI bar configuration when adding regionsGurchetan Singh2019-03-01
| | | | | | | | | | | | | | | This removes add_memory_region and add_io_region, and replaces it with the add_pci_bar function. BUG=chromium:924405 TEST=boot VM Change-Id: Ifc637d174d3f8b1255cf13725a1a224b4cdf0a30 Reviewed-on: https://chromium-review.googlesource.com/1480741 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* devices: pci: define a PCI bar configuration structGurchetan Singh2019-03-01
| | | | | | | | | | | | | | | We want to support 64-bit BARs and some additional functionality is required. BUG=chromium:924405 TEST=compile Change-Id: I06aba41b6dfb9649437a417a32cb450d19d0d937 Reviewed-on: https://chromium-review.googlesource.com/1480740 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* error: Print errors using Display implDavid Tolnay2019-02-20
| | | | | | | | | | | | | | | | | | | | | | | | | I have been running into Debug-printed error messages too often and needing to look up in the source code each level of nested errors to find out from the comment on the error variant what the short name of the variant means in human terms. Worse, many errors (like the one shown below) already had error strings written but were being printed from the calling code in the less helpful Debug representation anyway. Before: [ERROR:src/main.rs:705] The architecture failed to build the vm: NoVarEmpty After: [ERROR:src/main.rs:705] The architecture failed to build the vm: /var/empty doesn't exist, can't jail devices. TEST=cargo check --all-features TEST=FEATURES=test emerge-amd64-generic crosvm Change-Id: I77122c7d6861b2d610de2fff718896918ab21e10 Reviewed-on: https://chromium-review.googlesource.com/1469225 Commit-Ready: David Tolnay <dtolnay@chromium.org> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* devices: Add an Ac97 PCI deviceDylan Reid2019-01-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Ac97 device provides the guest with an audio playback device. All input devices are stubbed out. Only playback at 48kHz is supported. The device is emulated by `Ac97Dev` which interfaces with the PCI bus. `Ac97Dev` uses `Ac97` to drive audio functions and emulate the device registers. Physical Ac97 devices consist of two parts, the bus master and a mixer. These two sets of registers are emulated by the `Ac97BusMaster` and `Ac97Mixer` structures. `Ac97BusMaster` handles audio samples and uses `Ac97Mixer` to determine the configuration of the audio backend. BUG=chromium:781398 TEST=crosvm run --disable-sandbox --null-audio --rwdisk gentoo.ext4 -c2 -m2048 -p 'root=/dev/vda snd_intel8x0.inside_vm=1 snd_intel8x0.ac97_clock=48000' vmlinux.bin and play audio with aplay -d2 -Dhw:0,0 -f dat /dev/urandom CQ-DEPEND=CL:1402264 CQ-DEPEND=CL:1421588 CQ-DEPEND=CL:1433794 CQ-DEPEND=CL:1432835 Change-Id: I9985ffad753bccc1bf468ebbdacec0876560a5e0 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1366544 Commit-Ready: Chih-Yang Hsia <paulhsia@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Chih-Yang Hsia <paulhsia@chromium.org> Reviewed-by: Chih-Yang Hsia <paulhsia@chromium.org>
* crosvm: add debug labels to devices for improved SIGCHLD logsZach Reizner2019-01-26
| | | | | | | | | | | | | | | | | | | Each device (Bus, Pci, Proxy, etc), gets a debug label associated with it. When a child is spawned, the debug label for it is stored in a map with the child's pid as the key. If a SIGCHLD is handled, this map is used to print a more helpful message about exactly which child died. BUG=None TEST=run with sandboxing and a faulty child device check logs for message about child died the child should have a debug label Change-Id: I61fbbee0a8e701249533a7a3a6a1ad48840f12e5 Reviewed-on: https://chromium-review.googlesource.com/1432835 Commit-Ready: Chih-Yang Hsia <paulhsia@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Zach Reizner <zachr@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* devices: add on_sandboxedJingkui Wang2018-12-25
| | | | | | | | | | | | | | | | On sandboxed will be invoked when the device is sandboxed. Device implementation could do initialization here. It does not need to return fd opened here to keep fds. BUG=None TEST=local build and run Change-Id: I42c2b3cae3a87dd54f02e77b8cd10766309a0770 Reviewed-on: https://chromium-review.googlesource.com/1327513 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Jingkui Wang <jkwang@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org> Reviewed-by: Zach Reizner <zachr@chromium.org>
* sync: Mutex type with methods that panic instead of return errorDavid Tolnay2018-12-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds a crate `sync` containing a type sync::Mutex which wraps the standard library Mutex and mirrors the same methods, except that they panic where the standard library would return a PoisonError. This API codifies our error handling strategy around poisoned mutexes in crosvm. - Crosvm releases are built with panic=abort so poisoning never occurs. A panic while a mutex is held (or ever) takes down the entire process. Thus we would like for code not to have to consider the possibility of poison. - We could ask developers to always write `.lock().unwrap()` on a standard library mutex. However, we would like to stigmatize the use of unwrap. It is confusing to permit unwrap but only on mutex lock results. During code review it may not always be obvious whether a particular unwrap is unwrapping a mutex lock result or a different error that should be handled in a more principled way. Developers should feel free to use sync::Mutex anywhere in crosvm that they would otherwise be using std::sync::Mutex. TEST=boot linux Change-Id: I9727b6f8fee439edb4a8d52cf19d59acf04d990f Reviewed-on: https://chromium-review.googlesource.com/1359923 Commit-Ready: David Tolnay <dtolnay@chromium.org> Tested-by: David Tolnay <dtolnay@chromium.org> Reviewed-by: Zach Reizner <zachr@chromium.org>
* lint: Resolve the easier clippy lintsDavid Tolnay2018-12-03
| | | | | | | | | | | | | | | | | | | | Hopefully the changes are self-explanatory and uncontroversial. This eliminates much of the noise from `cargo clippy` and, for my purposes, gives me a reasonable way to use it as a tool when writing and reviewing code. Here is the Clippy invocation I was using: cargo +nightly clippy -- -W clippy::correctness -A renamed_and_removed_lints -Aclippy::{blacklisted_name,borrowed_box,cast_lossless,cast_ptr_alignment,enum_variant_names,identity_op,if_same_then_else,mut_from_ref,needless_pass_by_value,new_without_default,new_without_default_derive,or_fun_call,ptr_arg,should_implement_trait,single_match,too_many_arguments,trivially_copy_pass_by_ref,unreadable_literal,unsafe_vector_initialization,useless_transmute} TEST=cargo check --features wl-dmabuf,gpu,usb-emulation TEST=boot linux Change-Id: I55eb1b4a72beb2f762480e3333a921909314a0a2 Reviewed-on: https://chromium-review.googlesource.com/1356911 Commit-Ready: David Tolnay <dtolnay@chromium.org> Tested-by: David Tolnay <dtolnay@chromium.org> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: Remove duplicated doc comments in impl blockDavid Tolnay2018-12-02
| | | | | | | | | | | | | | | | These duplicate the doc comments found in `trait PciDevice`. I am removing them because a sensible reader would already assume that they have fallen out of sync with the doc comments in the trait, and thus refer to the trait definition anyway. TEST=none Change-Id: Id86936a6f2a1b6c78a000b107bb4fc8ed78e40f9 Reviewed-on: https://chromium-review.googlesource.com/1355350 Commit-Ready: David Tolnay <dtolnay@chromium.org> Tested-by: David Tolnay <dtolnay@chromium.org> Reviewed-by: Jingkui Wang <jkwang@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: support level-triggered interruptsDaniel Verkamp2018-10-29
| | | | | | | | | | | | | | | | Register the irqfd with resample support so that we can correctly emulate level-triggered interrupts. This requires each PciDevice to listen for interrupt_resample events and re-assert the IRQ eventfd if it should still be active. BUG=None TEST=Boot crosvm on x86-64 and arm devices Change-Id: I5cf8d1d1705cf675b453962c00d2d606801fee91 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1298654 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: make PCI work in --disable-sandbox modeDaniel Verkamp2018-10-19
| | | | | | | | | | | | | Make the Minijail part of the PCI device tuple optional so that an empty jail is not created for --disable-sandbox. BUG=None TEST=Boot crosvm in both --multiprocess and --disable-sandbox modes Change-Id: Ibb3f2dbf33ca19910ee7448ea823b2772e09ecc5 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1290289 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* arch: add virtio-pci eventfds with exact matchDaniel Verkamp2018-10-11
| | | | | | | | | | | | | | | | | | | | The virtio PCI spec (4.1.5.2 Notifying The Device) says: "The driver notifies the device by writing the 16-bit virtqueue index of this virtqueue to the Queue Notify address." We were previously registering the notify address specifying NoDatamatch; switch this to a 16-bit match of the queue index to follow the specification. BUG=chromium:854766 TEST=Boot crosvm with virtio devices converted to PCI Change-Id: Ic950a8c7751268f7fcc21d5c37b0afc859f1e6d0 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1265861 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* cargo fmt all source codeZach Reizner2018-10-09
| | | | | | | | | | | | | | Now that cargo fmt has landed, run it over everything at once to bring rust source to the standard formatting. TEST=cargo test BUG=None Change-Id: Ic95a48725e5a40dcbd33ba6d5aef2bd01e91865b Reviewed-on: https://chromium-review.googlesource.com/1259287 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Zach Reizner <zachr@chromium.org> Reviewed-by: Zach Reizner <zachr@chromium.org>
* devices: pci: add MMIO config access mechanismDaniel Verkamp2018-10-01
| | | | | | | | | This will be used on ARM. Change-Id: I61206b761f49f963f0cce706268379ceae1a0239 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1241540 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: refactor config access mechanismDaniel Verkamp2018-10-01
| | | | | | | | | | | | The current PciRoot is only workable for the legacy I/O port 0xCF8 access mechanism; factor out the config access mechanism part of PciRoot into PciConfigIo so that we can add a MMIO-based access mechanism for ARM. Change-Id: I87756b0ab31070d8717c76d419957bf5ea5d75ad Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1241539 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: make more registers read onlyDaniel Verkamp2018-10-01
| | | | | | | | | | Most of PCI configuration space should be read only; initialize the writable_bits field accordingly. Change-Id: I67f93d81cfbac6000db51663bdf76e54aeac08f3 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1240659 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: ignore writable_bits when adding capsDaniel Verkamp2018-10-01
| | | | | | | | | | | | | The add_capability() function was using the normal PCI configuration write_byte() function, which enforces read-only regions. This won't work once the appropriate regions of config space are marked as read only in the following commit, so add an internal-only helper function to access bytes without applying writable_bits. Change-Id: If61f79cd80950bf517d69c18aaf98c2e76841a56 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1240658 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: fix add_bar return valueDylan Reid2018-10-01
| | | | | | | | | | Return the BAR number rather than the register offset within PCI config space. Change-Id: I6e965c5fe7218abe6986b461731f18abb34894c1 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1240653 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: add ioeventfds to PciDevice traitDylan Reid2018-10-01
| | | | | | | | | | | | VirtioDevices and potentially others need to register ioeventfds that will be triggered when guests write to certain addresses. Allow PciDevices to return an array of ioeventfds that the VM can install. Change-Id: I2524c4e8c04f75a8d7868cac998304aecbb29c40 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1237360 Commit-Ready: Daniel Verkamp <dverkamp@chromium.org> Tested-by: Daniel Verkamp <dverkamp@chromium.org>
* devices: pci: add keep_fds to PciDeviceDaniel Verkamp2018-10-01
| | | | | | | | | | PciDevice implementations will have file descriptors that need to be preserved across the minijail fork. Change-Id: I0b1f5b827b55c4d8960ffa95331b82f9c692f304 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1237359 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: add Programming Interface to deviceDaniel Verkamp2018-10-01
| | | | | | | | | | | | PCI class codes are made up of three fields: class, subclass, and programming interface. Some class/subclass combinations do not define any programming interfaces, so add an optional parameter to specify the value and use 0 if it is not provided. Change-Id: Ib4000eafe2d7d003ed5753d7b0ea05e16fd06130 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1237358 Reviewed-by: Dylan Reid <dgreid@chromium.org>
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-06-29 11:55:24 +0000