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path: root/devices/src/pci
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* move pci root creation to archDylan Reid2018-10-01
| | | | | | | | | | passing everything in to the pci code is getting annoying. Instead build it up in arch which already has access to all the needed resources. Change-Id: If42f994443c4f11152fca8da16f27fa4cd80580d Reviewed-on: https://chromium-review.googlesource.com/1237357 Commit-Ready: Daniel Verkamp <dverkamp@chromium.org> Tested-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* fix warning and bit rotted tests uncovered by kokoroZach Reizner2018-09-22
| | | | | | | | | | | TEST=run kokoro presubmit BUG=None Change-Id: I301551f8f58263f1a8b7a8276867881cb17517ab Reviewed-on: https://chromium-review.googlesource.com/1236889 Commit-Ready: Zach Reizner <zachr@chromium.org> Tested-by: Zach Reizner <zachr@chromium.org> Reviewed-by: Stephen Barber <smbarber@chromium.org>
* devices: pci: add subsystem vendor and device IDDylan Reid2018-09-13
| | | | | | | | | | | The virtio PCI specification places requirements on the PCI subsystem IDs, so allow PCI devices to specify them in PciConfiguration. Change-Id: I70bc6ad4333ba3601db2831fef03483bcaea70ff Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1208156 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: fix capability mask in status regDylan Reid2018-09-10
| | | | | | | | | | | The status register is actually the high 16 bits of register index STATUS_REG (1). Adjust the STATUS_REG_CAPABILITIES_USED_MASK value accordingly so it is bit 4 within the high 16 bits. Change-Id: I3fb695a577bae754eda5640224ef335c44b119eb Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1208152 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* pci: add tests for add_capability()Daniel Verkamp2018-09-05
| | | | | | | | | | | | | | | | | | | Also fix the misleading add_capability() comment. The standard PCI capability header is just two bytes (capability type and next pointer); the length byte is only part of the vendor-specific capability (09h). More importantly, the current implementation of add_capability() already inserts the two-byte standard header, so the caller should not provide it as part of cap_data. BUG=None TEST=cargo test -p devices Change-Id: Id3517d021bfe29d08ff664d66455b15cf07af1d1 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1197069 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* Remove sync requirements of pci device traitJingkui Wang2018-08-29
| | | | | | | | | | | | | It's not needed. BUG=chromium:831850 TEST=cargo test Change-Id: I7e38590271ec14db422f5f3421302e98a2ca19ab Reviewed-on: https://chromium-review.googlesource.com/1194317 Commit-Ready: Jingkui Wang <jkwang@google.com> Tested-by: Jingkui Wang <jkwang@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* Add capabilities to PCI configuration spaceDylan Reid2018-08-09
| | | | | | | | | Allow PCI devices to specify the capabilities they have. Change-Id: I0730fb18dc71aa252da0903f4273e8d922ee2b8d Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1157440 Reviewed-by: Jingkui Wang <jkwang@google.com>
* pci: Add serial bus subclassJingkui Wang2018-07-27
| | | | | | | | | | | | | Add serial bus subclass BUG=chromium:831850 TEST=cargo test Change-Id: Iffd7a27b5cb423c928f0108b16fb58558cf7bcd4 Reviewed-on: https://chromium-review.googlesource.com/1152212 Commit-Ready: Jingkui Wang <jkwang@google.com> Tested-by: Jingkui Wang <jkwang@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci - Add a PCI root bridgeDylan Reid2018-07-19
| | | | | | | | | | | `PciRoot` represents the root PCI bridge for the system and manages PCI devices attached to it. The root bridge has its own set of configuration registers. Change-Id: I2b15630cf5a0fc5938e66986a65782c6939fcf55 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072577 Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
* devices: pci - Add PciDeviceDylan Reid2018-07-11
| | | | | | | | | | | The PciDevice trait represents any PciDevice. It provides access to configuration registers and BAR space. Change-Id: Ie18cb16b8bd97f9b70af05ebfebbfc612ce18494 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072575 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Sonny Rao <sonnyrao@chromium.org>
* devices: pci - Add PciConfigurationDylan Reid2018-07-11
| | | | | | | | | | | | PciConfiguration manages the PCI configuration space registers for a PCI device or bridge. Add accessors and setters for the registers that need to be modified for basic PCI device enumeration. Change-Id: I4a5a71d55a3c5f7fb52ce81acef51cb4291130c8 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072574 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Zach Reizner <zachr@chromium.org>
* devices: Add pci_typesDylan Reid2018-07-11
Start PCI work by defining an enum to represent the four PCI interrupt lines. Change-Id: Ib95a4e4a03f0d6917ed2bed4b1afb97d18ff4f9e Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072573 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-07-01 15:29:44 +0000