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path: root/devices/src/pci/pci_configuration.rs
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* devices: pci: replace byteorder with from_le_bytes()Daniel Verkamp2019-08-26
| | | | | | | | | | | | | | Use the standardized from_le_bytes() functions rather than the byteorder crate. BUG=None TEST=./build_test Change-Id: I07a062bf63c5d3ae1e25f403713bf9a1677e8cba Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1761155 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Zach Reizner <zachr@chromium.org>
* devices: silence unused code warning in PCIDaniel Verkamp2019-07-10
| | | | | | | | | | | | | | | | Now that nothing uses the PCI-to-PCI bridge device type, the compiler warns that it is never constructed. Mark the PciHeaderType enum to allow this, since the enum is public and could be constructed outside this file. BUG=None TEST=./build_test Change-Id: I6832996c4e00a33cc1ba88d97fede65b226cbfc5 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1691239 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* pci: Let device could trap pci config read/writeXiong Zhang2019-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently device impliments PciDevice trait, it will return config register to bus trait at pci cfg r/w, then BusDevice trait on behave of device to do actual pci config r/w. But vfio device need to handle the pci config r/w by itself, as vfio device need to transfer this request to kernel. For pci config read, this patch delete PciDevice->config_registers(), and add PciDevice->read_config_register(), then BusDevice-> config_register_read() call PciDevice->read_config_register(), finally Device could trap the PciConfig Read. For pci config write, it is similiar with pci config read. But the common code is moved into PciConfiguration. BUG=none TEST=none Change-Id: Ie6bd3a8c94f523d6fb1ef3d1e97d087bb0407d9f Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1580457 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>
* devices: pci: preserve read-only bits in write_regDaniel Verkamp2019-06-25
| | | | | | | | | | | | | | | | | | The 32-bit write_reg() function for PCI configuration space masked off non-writable (read-only) bits from the incoming value, but it did not preserve the original bits from the register; this results in writes to read-only registers to clear all read-only bits to 0 instead. Preserve the original value of the read-only bits and add a test to verify that this works. BUG=None TEST=./build_test Change-Id: Icc67b429f17d519ec4e9090f8e0ce48aaff76491 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1660204 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: check BAR address alignmentDaniel Verkamp2019-06-25
| | | | | | | | | | | | | | | Each PCI BAR address must be aligned to at least its own size to allow the BAR sizing mechanism to work properly. Add a check in add_pci_bar() to enforce this. BUG=None TEST=Boot vm_kernel in crosvm Change-Id: Iee9d866c4982bd79935337682bd50b9205b95024 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1660203 Reviewed-by: Dylan Reid <dgreid@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com>
* resources+pci: allocator rework (allocation tags)Daniel Prilik2019-04-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | AddressAllocator now maintains a HashMap<Alloc, (u64, u64, u64)>, which uniquely maps a Allocation enum (e.g: PciBar(bus, dev, bar), GpuRenderNode, etc...) to it's address, size, and human-readable tag / description. The interface has also been modified to use Error instead of Option. Aside from improving debugging, tracking allocations will have numerous uses in the future. For example, when allocating guest memory over VmControl sockets, it will be possible to restrict allocations to pre-allocated slices of memory owned by the requesting device. To plumb through PCI information to PCI devices, this CL necessitated the addition of a PciDevice method called `assign_bus_dev`, which notifies PCI devices of their uniquely assigned Bus and Device numbers. BUG=chromium:936567 TEST=cargo test -p resources && cargo build --features="gpu gpu-forward" Change-Id: I8b4b0e32c6f3168138739249ede53d03143ee5c3 Reviewed-on: https://chromium-review.googlesource.com/1536207 Commit-Ready: Daniel Prilik <prilik@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Zach Reizner <zachr@chromium.org>
* edition: Fill in macro importsDavid Tolnay2019-04-15
| | | | | | | | | | | | | | | | | | | | Macros were previously imported through `#[macro_use] extern crate`, which is basically a glob import of all macros from the crate. As of 2018 edition of Rust, `extern crate` is no longer required and macros are imported individually like any other item from a dependency. This CL fills in all the appropriate macro imports that will allow us to remove our use of `extern crate` in a subsequent CL. TEST=cargo check --all-features --tests TEST=kokoro Change-Id: If2ec08b06b743abf5f62677c6a9927c3d5d90a54 Reviewed-on: https://chromium-review.googlesource.com/1565546 Commit-Ready: David Tolnay <dtolnay@chromium.org> Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
* edition: Use dyn syntax for trait objectsDavid Tolnay2019-04-08
| | | | | | | | | | | | | | | | | | | | | Found by running: `cargo rustc -- -D bare_trait_objects` Bare trait objects like `&Trait` and `Box<Trait>` are soft-deprecated in 2018 edition and will start warning at some point. As part of this, I replaced `Box<Trait + 'static>` with `Box<dyn Trait>` because the 'static bound is implied for boxed trait objects. TEST=cargo check --all-features TEST=cargo check --target aarch64-unknown-linux-gnu TEST=local kokoro Change-Id: I41c4f13530bece8a34a8ed1c1afd7035b8f86f19 Reviewed-on: https://chromium-review.googlesource.com/1513059 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
* pci: match pci cap structs with linux/virtio_pci.hDaniel Prilik2019-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VirtioPciCap omits the `cap_vndr` and `cap_next` fields from it's definition, deferring the instantiation of these bytes to the add_capability method in PCI configuration. There is even a comment on add_capability that mentions this omission. Unfortunately, comments tend not to be read, and mismatches between the linux headers and crosvm structures can result in some subtle and tricky to debug bugs, especially when implementing other types of virtio capabilties that subsume VirtioPciCap. Case in point, when implementing the VirtioPciShmCap (used by virtio-fs), this subtle mismatch resulted in a bug where an additional 2 bytes of padding were inserted between the `cap` member and the `offset_hi` member (see CL:1493014 for the exact struct). Since the cap_len field was instantiated using mem::sizeof Self, the additional padding just-so-happened to be the perfect ammount to sneak past the sanity checks in add_capabilities. The bug manifested itself by shifting over the length_hi field by 16 bits, resulting in much larger than expected cache sizes. This CL brings the VirtioPciCap structures in-line with their linux/virtio_pci.h counterparts, marking the structures as repr(C) (as opposed to repr(packed)) and leaving the cap_vndr and cap_next members in the struct, noting that they will be automatically populated in add_capability. BUG=chromium:936567 TEST=cargo test -p devices, boot vm Change-Id: Ia360e532b58070372a52346e85dd4e30e81ace7a Reviewed-on: https://chromium-review.googlesource.com/1540397 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* edition: Update absolute paths to 2018 styleDavid Tolnay2019-03-13
| | | | | | | | | | | | | | | | | | | | | | | | | | This is an easy step toward adopting 2018 edition eventually, and will make any future CL that sets `edition = "2018"` this much smaller. The module system changes in Rust 2018 are described here: https://doc.rust-lang.org/edition-guide/rust-2018/module-system/path-clarity.html Generated by running: cargo fix --edition --all in each workspace, followed by bin/fmt. TEST=cargo check TEST=cargo check --all-features TEST=cargo check --target aarch64-unknown-linux-gnu Change-Id: I000ab5e69d69aa222c272fae899464bbaf65f6d8 Reviewed-on: https://chromium-review.googlesource.com/1513054 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: David Tolnay <dtolnay@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
* devices: PCI: fix underflow for 64 bit BAR configDaniel Prilik2019-03-08
| | | | | | | | | | | | | | | underflow occurs when configuring a 64 bit register with a <33 bit address. BUG=chromium:924405 TEST=boot VM Change-Id: I53a309b7bff3c91012bacb12d9fc9f8ceed68699 Reviewed-on: https://chromium-review.googlesource.com/1493011 Commit-Ready: Daniel Prilik <prilik@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-by: Zach Reizner <zachr@chromium.org>
* PCI: Return results from pci setup functionsDylan Reid2019-03-06
| | | | | | | | | | | | | | | | Enough failure cases have been added to `add_pci_bar` and `add_pci_capabilities` that they should return unique errors instead of an `Option`. BUG=none TEST=cargo test in devices Signed-off-by: Dylan Reid <dgreid@chromium.org> Change-Id: Ice2a06d2944011f95707f113f9d709da15c90cfe Reviewed-on: https://chromium-review.googlesource.com/1497740 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* devices: use PCI bar configuration when adding regionsGurchetan Singh2019-03-01
| | | | | | | | | | | | | | | This removes add_memory_region and add_io_region, and replaces it with the add_pci_bar function. BUG=chromium:924405 TEST=boot VM Change-Id: Ifc637d174d3f8b1255cf13725a1a224b4cdf0a30 Reviewed-on: https://chromium-review.googlesource.com/1480741 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* devices: pci: define a PCI bar configuration structGurchetan Singh2019-03-01
| | | | | | | | | | | | | | | We want to support 64-bit BARs and some additional functionality is required. BUG=chromium:924405 TEST=compile Change-Id: I06aba41b6dfb9649437a417a32cb450d19d0d937 Reviewed-on: https://chromium-review.googlesource.com/1480740 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
* lint: Resolve the easier clippy lintsDavid Tolnay2018-12-03
| | | | | | | | | | | | | | | | | | | | Hopefully the changes are self-explanatory and uncontroversial. This eliminates much of the noise from `cargo clippy` and, for my purposes, gives me a reasonable way to use it as a tool when writing and reviewing code. Here is the Clippy invocation I was using: cargo +nightly clippy -- -W clippy::correctness -A renamed_and_removed_lints -Aclippy::{blacklisted_name,borrowed_box,cast_lossless,cast_ptr_alignment,enum_variant_names,identity_op,if_same_then_else,mut_from_ref,needless_pass_by_value,new_without_default,new_without_default_derive,or_fun_call,ptr_arg,should_implement_trait,single_match,too_many_arguments,trivially_copy_pass_by_ref,unreadable_literal,unsafe_vector_initialization,useless_transmute} TEST=cargo check --features wl-dmabuf,gpu,usb-emulation TEST=boot linux Change-Id: I55eb1b4a72beb2f762480e3333a921909314a0a2 Reviewed-on: https://chromium-review.googlesource.com/1356911 Commit-Ready: David Tolnay <dtolnay@chromium.org> Tested-by: David Tolnay <dtolnay@chromium.org> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* cargo fmt all source codeZach Reizner2018-10-09
| | | | | | | | | | | | | | Now that cargo fmt has landed, run it over everything at once to bring rust source to the standard formatting. TEST=cargo test BUG=None Change-Id: Ic95a48725e5a40dcbd33ba6d5aef2bd01e91865b Reviewed-on: https://chromium-review.googlesource.com/1259287 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Zach Reizner <zachr@chromium.org> Reviewed-by: Zach Reizner <zachr@chromium.org>
* devices: pci: make more registers read onlyDaniel Verkamp2018-10-01
| | | | | | | | | | Most of PCI configuration space should be read only; initialize the writable_bits field accordingly. Change-Id: I67f93d81cfbac6000db51663bdf76e54aeac08f3 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1240659 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: ignore writable_bits when adding capsDaniel Verkamp2018-10-01
| | | | | | | | | | | | | The add_capability() function was using the normal PCI configuration write_byte() function, which enforces read-only regions. This won't work once the appropriate regions of config space are marked as read only in the following commit, so add an internal-only helper function to access bytes without applying writable_bits. Change-Id: If61f79cd80950bf517d69c18aaf98c2e76841a56 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1240658 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: fix add_bar return valueDylan Reid2018-10-01
| | | | | | | | | | Return the BAR number rather than the register offset within PCI config space. Change-Id: I6e965c5fe7218abe6986b461731f18abb34894c1 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1240653 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: add Programming Interface to deviceDaniel Verkamp2018-10-01
| | | | | | | | | | | | PCI class codes are made up of three fields: class, subclass, and programming interface. Some class/subclass combinations do not define any programming interfaces, so add an optional parameter to specify the value and use 0 if it is not provided. Change-Id: Ib4000eafe2d7d003ed5753d7b0ea05e16fd06130 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1237358 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* fix warning and bit rotted tests uncovered by kokoroZach Reizner2018-09-22
| | | | | | | | | | | TEST=run kokoro presubmit BUG=None Change-Id: I301551f8f58263f1a8b7a8276867881cb17517ab Reviewed-on: https://chromium-review.googlesource.com/1236889 Commit-Ready: Zach Reizner <zachr@chromium.org> Tested-by: Zach Reizner <zachr@chromium.org> Reviewed-by: Stephen Barber <smbarber@chromium.org>
* devices: pci: add subsystem vendor and device IDDylan Reid2018-09-13
| | | | | | | | | | | The virtio PCI specification places requirements on the PCI subsystem IDs, so allow PCI devices to specify them in PciConfiguration. Change-Id: I70bc6ad4333ba3601db2831fef03483bcaea70ff Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1208156 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci: fix capability mask in status regDylan Reid2018-09-10
| | | | | | | | | | | The status register is actually the high 16 bits of register index STATUS_REG (1). Adjust the STATUS_REG_CAPABILITIES_USED_MASK value accordingly so it is bit 4 within the high 16 bits. Change-Id: I3fb695a577bae754eda5640224ef335c44b119eb Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1208152 Reviewed-by: Dylan Reid <dgreid@chromium.org>
* pci: add tests for add_capability()Daniel Verkamp2018-09-05
| | | | | | | | | | | | | | | | | | | Also fix the misleading add_capability() comment. The standard PCI capability header is just two bytes (capability type and next pointer); the length byte is only part of the vendor-specific capability (09h). More importantly, the current implementation of add_capability() already inserts the two-byte standard header, so the caller should not provide it as part of cap_data. BUG=None TEST=cargo test -p devices Change-Id: Id3517d021bfe29d08ff664d66455b15cf07af1d1 Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1197069 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* Add capabilities to PCI configuration spaceDylan Reid2018-08-09
| | | | | | | | | Allow PCI devices to specify the capabilities they have. Change-Id: I0730fb18dc71aa252da0903f4273e8d922ee2b8d Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1157440 Reviewed-by: Jingkui Wang <jkwang@google.com>
* pci: Add serial bus subclassJingkui Wang2018-07-27
| | | | | | | | | | | | | Add serial bus subclass BUG=chromium:831850 TEST=cargo test Change-Id: Iffd7a27b5cb423c928f0108b16fb58558cf7bcd4 Reviewed-on: https://chromium-review.googlesource.com/1152212 Commit-Ready: Jingkui Wang <jkwang@google.com> Tested-by: Jingkui Wang <jkwang@google.com> Reviewed-by: Dylan Reid <dgreid@chromium.org>
* devices: pci - Add PciConfigurationDylan Reid2018-07-11
PciConfiguration manages the PCI configuration space registers for a PCI device or bridge. Add accessors and setters for the registers that need to be modified for basic PCI device enumeration. Change-Id: I4a5a71d55a3c5f7fb52ce81acef51cb4291130c8 Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072574 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Zach Reizner <zachr@chromium.org>
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-06-26 18:21:41 +0000