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Diffstat (limited to 'devices/src/virtio/virtio_pci_common_config.rs')
-rw-r--r--devices/src/virtio/virtio_pci_common_config.rs7
1 files changed, 4 insertions, 3 deletions
diff --git a/devices/src/virtio/virtio_pci_common_config.rs b/devices/src/virtio/virtio_pci_common_config.rs
index 977e2c0..d1ea3e8 100644
--- a/devices/src/virtio/virtio_pci_common_config.rs
+++ b/devices/src/virtio/virtio_pci_common_config.rs
@@ -118,10 +118,11 @@ impl VirtioPciCommonConfig {
 
     fn read_common_config_word(&self, offset: u64, queues: &[Queue]) -> u16 {
         match offset {
-            0x10 => 0,                   // TODO msi-x (crbug/854765): self.msix_config,
+            0x10 => self.msix_config,
             0x12 => queues.len() as u16, // num_queues
             0x16 => self.queue_select,
             0x18 => self.with_queue(queues, |q| q.size).unwrap_or(0),
+            0x1a => self.with_queue(queues, |q| q.vector).unwrap_or(0),
             0x1c => {
                 if self.with_queue(queues, |q| q.ready).unwrap_or(false) {
                     1
@@ -136,10 +137,10 @@ impl VirtioPciCommonConfig {
 
     fn write_common_config_word(&mut self, offset: u64, value: u16, queues: &mut [Queue]) {
         match offset {
-            0x10 => (), // TODO msi-x (crbug/854765): self.msix_config = value,
+            0x10 => self.msix_config = value,
             0x16 => self.queue_select = value,
             0x18 => self.with_queue_mut(queues, |q| q.size = value),
-            0x1a => (), // TODO msi-x (crbug/854765): self.with_queue_mut(queues, |q| q.msix_vector = v),
+            0x1a => self.with_queue_mut(queues, |q| q.vector = value),
             0x1c => self.with_queue_mut(queues, |q| q.ready = value == 1),
             _ => {
                 warn!("invalid virtio register word write: 0x{:x}", offset);