diff options
author | Zide Chen <zide.chen@intel.corp-partner.google.com> | 2019-09-26 11:40:49 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-10-24 20:46:40 +0000 |
commit | d6be9614baea746efbc2744d7a914c95e315ea63 (patch) | |
tree | 6f7db5ac846f528fc97dd1e3b00c55754a6c28fe /devices/src/virtio/virtio_pci_common_config.rs | |
parent | 1f20497b86985bd927df9c171174a29cf47ce25f (diff) | |
download | crosvm-d6be9614baea746efbc2744d7a914c95e315ea63.tar crosvm-d6be9614baea746efbc2744d7a914c95e315ea63.tar.gz crosvm-d6be9614baea746efbc2744d7a914c95e315ea63.tar.bz2 crosvm-d6be9614baea746efbc2744d7a914c95e315ea63.tar.lz crosvm-d6be9614baea746efbc2744d7a914c95e315ea63.tar.xz crosvm-d6be9614baea746efbc2744d7a914c95e315ea63.tar.zst crosvm-d6be9614baea746efbc2744d7a914c95e315ea63.zip |
devices: finish the functions to enable MSI-X
- add a new field "vector" to struct Queue, which represents the entry number to the MSI-X Table. This can be used to find out the desired irqfd to inject MSI-X interrupts to the guest. - enable MSI-X when MSI-X Enable bit of the Message Control word is being set: allocate irqfd per MSI-X vector; register the irqfd to KVM; update GSI routing to KVM. - update GSI routing if the Message Data or Message Addr of individual MSI-X table Entry is being changed in run time. BUG=chromium:854765 TEST=cargo test -p devices Change-Id: I81533999ab6cd9ec5f111b256caf34077a4a7d1a Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com> Signed-off-by: Zide Chen <zide.chen@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1828338 Reviewed-by: Daniel Verkamp <dverkamp@chromium.org> Tested-by: Daniel Verkamp <dverkamp@chromium.org> Commit-Queue: Stephen Barber <smbarber@chromium.org>
Diffstat (limited to 'devices/src/virtio/virtio_pci_common_config.rs')
-rw-r--r-- | devices/src/virtio/virtio_pci_common_config.rs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/devices/src/virtio/virtio_pci_common_config.rs b/devices/src/virtio/virtio_pci_common_config.rs index 977e2c0..d1ea3e8 100644 --- a/devices/src/virtio/virtio_pci_common_config.rs +++ b/devices/src/virtio/virtio_pci_common_config.rs @@ -118,10 +118,11 @@ impl VirtioPciCommonConfig { fn read_common_config_word(&self, offset: u64, queues: &[Queue]) -> u16 { match offset { - 0x10 => 0, // TODO msi-x (crbug/854765): self.msix_config, + 0x10 => self.msix_config, 0x12 => queues.len() as u16, // num_queues 0x16 => self.queue_select, 0x18 => self.with_queue(queues, |q| q.size).unwrap_or(0), + 0x1a => self.with_queue(queues, |q| q.vector).unwrap_or(0), 0x1c => { if self.with_queue(queues, |q| q.ready).unwrap_or(false) { 1 @@ -136,10 +137,10 @@ impl VirtioPciCommonConfig { fn write_common_config_word(&mut self, offset: u64, value: u16, queues: &mut [Queue]) { match offset { - 0x10 => (), // TODO msi-x (crbug/854765): self.msix_config = value, + 0x10 => self.msix_config = value, 0x16 => self.queue_select = value, 0x18 => self.with_queue_mut(queues, |q| q.size = value), - 0x1a => (), // TODO msi-x (crbug/854765): self.with_queue_mut(queues, |q| q.msix_vector = v), + 0x1a => self.with_queue_mut(queues, |q| q.vector = value), 0x1c => self.with_queue_mut(queues, |q| q.ready = value == 1), _ => { warn!("invalid virtio register word write: 0x{:x}", offset); |