devices: Start to implement IOAPIC.

This change implements service_irq, end_of_interrupt, and just enough to
add some basic tests for those.

Still TODO: Interrupt routing (and tests for that) and tests that
require additional functionality.

BUG=chromium:908689
TEST=Unit tests in file. Integration testing is blocked on rest of split-irqchip being implemented.

Change-Id: Ia8418f9a8bec92b53d99cdafb92f05f82eafa2b1
Reviewed-on: https://chromium-review.googlesource.com/1558935
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Miriam Zimmerman <mutexlox@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: David Tolnay <dtolnay@chromium.org>

1 files changed, 13 insertions, 29 deletions

diff --git a/devices/src/split_irqchip_common.rs b/devices/src/split_irqchip_common.rs
index 6a722e2..65ba809 100644
--- a/devices/src/split_irqchip_common.rs
+++ b/devices/src/split_irqchip_common.rs
@@ -20,21 +20,22 @@ pub enum TriggerMode {
     Level = 1,
 }
 
-#[derive(Clone, Copy, PartialEq)]
+#[bitfield]
+#[derive(Debug, Clone, Copy, PartialEq)]
 pub enum DeliveryMode {
-    DeliveryModeFixed = 0b000,
-    DeliveryModeLowest = 0b001,
-    DeliveryModeSMI = 0b010,        // System management interrupt
-    DeliveryModeRemoteRead = 0b011, // This is no longer supported by intel.
-    DeliveryModeNMI = 0b100,        // Non maskable interrupt
-    DeliveryModeInit = 0b101,
-    DeliveryModeStartup = 0b110,
-    DeliveryModeExternal = 0b111,
+    Fixed = 0b000,
+    Lowest = 0b001,
+    SMI = 0b010,        // System management interrupt
+    RemoteRead = 0b011, // This is no longer supported by intel.
+    NMI = 0b100,        // Non maskable interrupt
+    Init = 0b101,
+    Startup = 0b110,
+    External = 0b111,
 }
 
 #[bitfield]
 #[derive(Clone, Copy, PartialEq)]
-pub struct MsiAddressMessageNonRemappable {
+pub struct MsiAddressMessage {
     reserved: BitField2,
     #[bits = 1]
     destination_mode: DestinationMode,
@@ -47,27 +48,10 @@ pub struct MsiAddressMessageNonRemappable {
 
 #[bitfield]
 #[derive(Clone, Copy, PartialEq)]
-pub struct MsiAddressMessageRemappable {
-    reserved: BitField2,
-    handle_hi: BitField1, // Bit 15 of handle
-    shv: BitField1,
-    interrupt_format: BitField1,
-    handle_low: BitField15, // Bits 0-14 of handle.
-    // According to Intel's implementation of MSI, these bits must always be 0xfee.
-    always_0xfee: BitField12,
-}
-
-#[derive(Clone, Copy, PartialEq)]
-pub enum MsiAddressMessage {
-    NonRemappable(MsiAddressMessageNonRemappable),
-    Remappable(MsiAddressMessageRemappable),
-}
-
-#[bitfield]
-#[derive(Clone, Copy, PartialEq)]
 struct MsiDataMessage {
     vector: BitField8,
-    delivery_mode: BitField3,
+    #[bits = 3]
+    delivery_mode: DeliveryMode,
     reserved: BitField3,
     level: BitField1,
     #[bits = 1]