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author | Miriam Zimmerman <mutexlox@google.com> | 2019-03-15 16:54:25 -0700 |
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committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-20 08:52:41 -0700 |
commit | 63e3a83a37fe62fd0189a08ac178b7c2b74b91cb (patch) | |
tree | 0cd9703f530dd2394ca3e5c4150f37940e9554bb /devices/src/split_irqchip_common.rs | |
parent | 7e622edd00393dbd018f6d20039f8abfa945a287 (diff) | |
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Move split_irqchip_common to devices/.
Previously, code in devices/ couldn't use split_irqchip_common, since x86_64/ already has a dependency on devices/. TEST=Built. BUG=chromium:908689 Change-Id: I481514ae6bbd68e47feecc6f364ca8f4fd798e67 Reviewed-on: https://chromium-review.googlesource.com/1526762 Commit-Ready: Miriam Zimmerman <mutexlox@chromium.org> Tested-by: Miriam Zimmerman <mutexlox@chromium.org> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: David Tolnay <dtolnay@chromium.org>
Diffstat (limited to 'devices/src/split_irqchip_common.rs')
-rw-r--r-- | devices/src/split_irqchip_common.rs | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/devices/src/split_irqchip_common.rs b/devices/src/split_irqchip_common.rs new file mode 100644 index 0000000..6a722e2 --- /dev/null +++ b/devices/src/split_irqchip_common.rs @@ -0,0 +1,76 @@ +// Copyright 2019 The Chromium OS Authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. + +// Common constants and types used for Split IRQ chip devices (e.g. PIC, PIT, IOAPIC). + +use bit_field::*; + +#[bitfield] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum DestinationMode { + Physical = 0, + Logical = 1, +} + +#[bitfield] +#[derive(Clone, Copy, Debug, PartialEq)] +pub enum TriggerMode { + Edge = 0, + Level = 1, +} + +#[derive(Clone, Copy, PartialEq)] +pub enum DeliveryMode { + DeliveryModeFixed = 0b000, + DeliveryModeLowest = 0b001, + DeliveryModeSMI = 0b010, // System management interrupt + DeliveryModeRemoteRead = 0b011, // This is no longer supported by intel. + DeliveryModeNMI = 0b100, // Non maskable interrupt + DeliveryModeInit = 0b101, + DeliveryModeStartup = 0b110, + DeliveryModeExternal = 0b111, +} + +#[bitfield] +#[derive(Clone, Copy, PartialEq)] +pub struct MsiAddressMessageNonRemappable { + reserved: BitField2, + #[bits = 1] + destination_mode: DestinationMode, + redirection_hint: BitField1, + reserved_2: BitField8, + destination_id: BitField8, + // According to Intel's implementation of MSI, these bits must always be 0xfee. + always_0xfee: BitField12, +} + +#[bitfield] +#[derive(Clone, Copy, PartialEq)] +pub struct MsiAddressMessageRemappable { + reserved: BitField2, + handle_hi: BitField1, // Bit 15 of handle + shv: BitField1, + interrupt_format: BitField1, + handle_low: BitField15, // Bits 0-14 of handle. + // According to Intel's implementation of MSI, these bits must always be 0xfee. + always_0xfee: BitField12, +} + +#[derive(Clone, Copy, PartialEq)] +pub enum MsiAddressMessage { + NonRemappable(MsiAddressMessageNonRemappable), + Remappable(MsiAddressMessageRemappable), +} + +#[bitfield] +#[derive(Clone, Copy, PartialEq)] +struct MsiDataMessage { + vector: BitField8, + delivery_mode: BitField3, + reserved: BitField3, + level: BitField1, + #[bits = 1] + trigger: TriggerMode, + reserved2: BitField16, +} |