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author | Alyssa Ross <hi@alyssa.is> | 2020-03-17 05:29:05 +0000 |
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committer | Alyssa Ross <hi@alyssa.is> | 2020-03-17 05:51:44 +0000 |
commit | a26247863a962e5fbc331dd62f770501f7d86145 (patch) | |
tree | dd284e782fd9fa4a3f19d33fd6df57db2f34421e /devices/src/pci | |
parent | fbc11f247fa0d58f050daf02a8e9aaa4cab02caf (diff) | |
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devices: add missing PCI derives
A lot of the PCI types had some derives missing that it would be quite clearly beneficial to add, and I think it's better to add them all now than piecemeal as required.
Diffstat (limited to 'devices/src/pci')
-rw-r--r-- | devices/src/pci/pci_configuration.rs | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/devices/src/pci/pci_configuration.rs b/devices/src/pci/pci_configuration.rs index ebfa2a6..ff2da1a 100644 --- a/devices/src/pci/pci_configuration.rs +++ b/devices/src/pci/pci_configuration.rs @@ -25,7 +25,7 @@ const INTERRUPT_LINE_PIN_REG: usize = 15; /// Represents the types of PCI headers allowed in the configuration registers. #[allow(dead_code)] -#[derive(Copy, Clone)] +#[derive(Copy, Clone, Debug)] pub enum PciHeaderType { Device, Bridge, @@ -33,7 +33,7 @@ pub enum PciHeaderType { /// Classes of PCI nodes. #[allow(dead_code)] -#[derive(Copy, Clone)] +#[derive(Copy, Clone, Debug)] pub enum PciClassCode { TooOld, MassStorage, @@ -70,7 +70,7 @@ pub trait PciSubclass { /// Subclasses of the MultimediaController class. #[allow(dead_code)] -#[derive(Copy, Clone)] +#[derive(Copy, Clone, Debug, Eq, PartialEq)] pub enum PciMultimediaSubclass { VideoController = 0x00, AudioController = 0x01, @@ -87,7 +87,7 @@ impl PciSubclass for PciMultimediaSubclass { /// Subclasses of the BridgeDevice #[allow(dead_code)] -#[derive(Copy, Clone)] +#[derive(Copy, Clone, Debug, Eq, PartialEq)] pub enum PciBridgeSubclass { HostBridge = 0x00, IsaBridge = 0x01, @@ -111,7 +111,7 @@ impl PciSubclass for PciBridgeSubclass { /// Subclass of the SerialBus #[allow(dead_code)] -#[derive(Copy, Clone)] +#[derive(Copy, Clone, Debug, Eq, PartialEq)] pub enum PciSerialBusSubClass { Firewire = 0x00, ACCESSbus = 0x01, @@ -135,6 +135,7 @@ pub trait PciProgrammingInterface { } /// Types of PCI capabilities. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] pub enum PciCapabilityID { ListID = 0, PowerManagement = 0x01, @@ -177,20 +178,20 @@ pub struct PciConfiguration { } /// See pci_regs.h in kernel -#[derive(Copy, Clone, Debug, PartialEq)] +#[derive(Copy, Clone, Debug, Eq, PartialEq)] pub enum PciBarRegionType { Memory32BitRegion = 0, IORegion = 0x01, Memory64BitRegion = 0x04, } -#[derive(Copy, Clone)] +#[derive(Copy, Clone, Debug, Eq, PartialEq)] pub enum PciBarPrefetchable { NotPrefetchable = 0, Prefetchable = 0x08, } -#[derive(Copy, Clone)] +#[derive(Copy, Clone, Debug)] pub struct PciBarConfiguration { addr: u64, size: u64, |