devices: enable MSI-X for virtio-net and viotio-block devices

- signal_used_queue(): trigger MSI-X interrupts to the guest if MSI-X is
  enabled, otherwise trigger INTx interrupts
- enable MSI-X on vhost-net: allocate one vhost_interrupt for every
  MSI-X vector.

Performance wise, fio random R/W test on eve pixelbook:

           INTx          MSI-X      delta
fio write  8.13MiB/s    9.79MiB/s   +1.66MiB/s (+20%)
fio read   24.35MiB/s   29.3MiB/s   +4.95MiB/s (+20%)

For networking performance (TCP stream), test results on eve pixelbook:

             INTx            MSI-X          delta
iperf3       5.93Gbits/s     6.57Gbits/s    +0.64Gbits/s (+10.7%)
iperf3 -R    5.68Gbits/s     7.37Gbits/s    +1.30Gbits/s (+22.8%)

iperf test results on VM launched from Ubuntu host (client sends only):

             INTx            MSI-X          delta
virtio-net   9.53Gbits/s     11.4 Gbits/s   +1.87Gbits/s (+19.5%)
vhost        28.34Gbits/s    44.43Gbits/s   +16.09Gbits/s (+56.7%)

BUG=chromium:854765
TEST=cargo test -p devices
TEST=tested virtio-net and block on Linux VM and eve pixelbook

Change-Id: Ic4952a094327e6b977f446def8209ea2f796878c
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.corp-partner.google.com>
Signed-off-by: Zide Chen <zide.chen@intel.corp-partner.google.com>
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/crosvm/+/1828340
Reviewed-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: Daniel Verkamp <dverkamp@chromium.org>
Tested-by: kokoro <noreply+kokoro@google.com>
Commit-Queue: Daniel Verkamp <dverkamp@chromium.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/devices/src/pci/msix.rs b/devices/src/pci/msix.rs
index 6110b72..368f8b7 100644
--- a/devices/src/pci/msix.rs
+++ b/devices/src/pci/msix.rs
@@ -83,7 +83,7 @@ impl MsixConfig {
     /// Check whether the Function Mask bit in Message Control word in set or not.
     /// if 1, all of the vectors associated with the function are masked,
     /// regardless of their per-vector Mask bit states.
-    /// If 0, each vector’s Mask bit determines whether the vector is masked or not.
+    /// If 0, each vector's Mask bit determines whether the vector is masked or not.
     pub fn masked(&self) -> bool {
         self.masked
     }
@@ -201,7 +201,7 @@ impl MsixConfig {
     /// For all accesses to MSI-X Table and MSI-X PBA fields, software must use aligned full
     /// DWORD or aligned full QWORD transactions; otherwise, the result is undefined.
     ///
-    ///             DWORD3            DWORD2      DWORD1            DWORD0
+    ///   location: DWORD3            DWORD2      DWORD1            DWORD0
     ///   entry 0:  Vector Control    Msg Data    Msg Upper Addr    Msg Addr
     ///   entry 1:  Vector Control    Msg Data    Msg Upper Addr    Msg Addr
     ///   entry 2:  Vector Control    Msg Data    Msg Upper Addr    Msg Addr
@@ -253,7 +253,7 @@ impl MsixConfig {
     ///     for the memory write transaction; different MSI-X vectors have
     ///     different Message Address values
     /// Message Data: the contents of this field specifies the data driven
-    ///     on AD[31::00] during the memory write transaction’s data phase.
+    ///     on AD[31::00] during the memory write transaction's data phase.
     /// Vector Control: only bit 0 (Mask Bit) is not reserved: when this bit
     ///     is set, the function is prohibited from sending a message using
     ///     this MSI-X Table entry.