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| author | Dylan Reid <dgreid@chromium.org> | 2018-07-10 17:07:58 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-10 17:17:36 -0700 |
| commit | 11809f60ab725d7f547b3c90663c0558cb881002 (patch) | |
| tree | fdc65acfbce47854895404c3536fb60e3e83ffe1 | |
| parent | bc8d9059abb23e8d4ca48662dcec454a03f5099d (diff) | |
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devices: pci: fix capability mask in status reg
The status register is actually the high 16 bits of register index STATUS_REG (1). Adjust the STATUS_REG_CAPABILITIES_USED_MASK value accordingly so it is bit 4 within the high 16 bits. Change-Id: I3fb695a577bae754eda5640224ef335c44b119eb Signed-off-by: Daniel Verkamp <dverkamp@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1208152 Reviewed-by: Dylan Reid <dgreid@chromium.org>
| -rw-r--r-- | devices/src/pci/pci_configuration.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/devices/src/pci/pci_configuration.rs b/devices/src/pci/pci_configuration.rs index f686c5d..bf7f57c 100644 --- a/devices/src/pci/pci_configuration.rs +++ b/devices/src/pci/pci_configuration.rs @@ -8,7 +8,7 @@ use pci::PciInterruptPin; const NUM_CONFIGURATION_REGISTERS: usize = 64; const STATUS_REG: usize = 1; -const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0000_0010; +const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0010_0000; const BAR0_REG: usize = 4; const BAR_IO_ADDR_MASK: u32 = 0xffff_fffc; const BAR_IO_BIT: u32 = 0x0000_0001; |